Add binman configuration to meson-gx-u-boot.dtsi to automate building
bootable images using amlimage.
Signed-off-by: Ferass El Hafidi <fundersc...@postmarketos.org>
---
arch/arm/dts/meson-gx-u-boot.dtsi | 142 ++++++++++++++++++++++++++++++++++++++
1 file changed, 142 insertions(+)
diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi
b/arch/arm/dts/meson-gx-u-boot.dtsi
index
9e0620f395e81048273690af4cee4b196ee7b0a7..d05f869c06ebefa08f5480327e4a72bbaa9a5e94
100644
--- a/arch/arm/dts/meson-gx-u-boot.dtsi
+++ b/arch/arm/dts/meson-gx-u-boot.dtsi
@@ -2,6 +2,7 @@
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Maxime Jourdan <mjour...@baylibre.com>
+ * Copyright (c) 2023 Ferass El Hafidi <fundersc...@postmarketos.org>
*/
/ {
@@ -15,6 +16,16 @@
soc {
bootph-all;
};
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+#if defined(CONFIG_BINMAN)
+ binman: binman {
+ multiple-images;
+ };
+#endif
};
&vpu {
@@ -30,3 +41,134 @@
<0x0 0xc883c000 0x0 0x1000>;
reg-names = "hdmitx", "hhi";
};
+
+#if defined(CONFIG_MESON_GX) && defined(CONFIG_BINMAN)
+/* binman configuration on GXBB and GXL */
+
+#if defined(CONFIG_MESON_GXBB)
+#define BL31_ADDR 0x10100000
+#else /* GXL */
+#define BL31_ADDR 0x05100000
+#endif
+
+/*
+ * On GXBB the base address of the SCP firmware doesn't matter as SPL will
+ * send the firmware to the SCP anyway, and can get the base address from the
+ * FIT. On GXL it matters, as BL31 is supposed to send the firmware, so set the
+ * base address to what GXL BL2 would load the binary to.
+ */
+#define SCP_ADDR 0x13c0000
+
+&binman {
+ u-boot-amlogic {
+ filename = "u-boot-meson-with-spl.bin";
+ pad-byte = <0xff>;
+
+ mkimage {
+ filename = "spl/u-boot-spl-signed.bin";
+#if defined(CONFIG_MESON_GXBB)
+ args = "-n", "gxbb", "-T", "amlimage";
+#elif defined(CONFIG_MESON_GXL)
+ args = "-n", "gxl", "-T", "amlimage";
+#endif
+
+ blob {
+ size = <0xb000>; /* The BootROM loads 48K max
(header is 4K) */
+ filename = "spl/u-boot-spl.bin";
+ };
+ };
+
+ fit: fit {
+ description = "ATF and U-Boot images";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,align = <512>;
+ offset = <CONFIG_SPL_PAD_TO>;
+
+ images {
+ u-boot {
+ description = "U-Boot";
+ type = "standalone";
+ os = "u-boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ entry = <CONFIG_TEXT_BASE>;
+
+ u-boot-nodtb {
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <BL31_ADDR>;
+ entry = <BL31_ADDR>;
+
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ hash {
+ algo = "sha256";
+ };
+ };
+
+ scp {
+ description = "SCP firmware";
+ type = "scp";
+ arch = "arm"; /* The Cortex-M core is
used as SCP */
+ compression = "none";
+ load = <SCP_ADDR>;
+
+ scp {
+ filename = "scp.bin";
+ };
+ hash {
+ /*
+ * The hash is used by the SCP
and passed to it
+ * by U-Boot SPL.
+ */
+ algo = "sha256";
+ };
+ };
+
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+ };
+
+ };
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+ @config-SEQ {
+ description = "NAME.dtb";
+ fdt = "fdt-SEQ";
+ firmware = "atf";
+ loadables = "scp", "u-boot";
+ };
+ };
+ };
+ };
+};
+
+&vpu {
+ /delete-property/ bootph-all;
+};
+
+&apb {
+ bootph-all;
+};
+
+&sd_emmc_b {
+ bootph-all;
+};
+
+&sd_emmc_c {
+ bootph-all;
+};
+#endif
--
2.51.0
