Upstream DP DT binding enforcing dp-connector and port description to
operate properly.
Co-developed-by: Rohit Visavalia <rohit.visava...@amd.com>
Signed-off-by: Rohit Visavalia <rohit.visava...@amd.com>
Co-developed-by: Nithish Kumar Naroju <nithishkumar.nar...@amd.com>
Signed-off-by: Nithish Kumar Naroju <nithishkumar.nar...@amd.com>
Signed-off-by: Michal Simek <michal.si...@amd.com>
---
arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 17 +++++++++++++++++
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 17 +++++++++++++++++
arch/arm/dts/zynqmp-zcu100-revC.dts | 18 ++++++++++++++++++
arch/arm/dts/zynqmp-zcu102-revA.dts | 18 ++++++++++++++++++
arch/arm/dts/zynqmp-zcu104-revA.dts | 18 ++++++++++++++++++
arch/arm/dts/zynqmp-zcu104-revC.dts | 18 ++++++++++++++++++
arch/arm/dts/zynqmp-zcu111-revA.dts | 18 ++++++++++++++++++
7 files changed, 124 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index fbacfa984d76..b92dcb86e87e 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -71,6 +71,17 @@
#clock-cells = <0>;
clock-frequency = <25000000>;
};
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -145,6 +156,12 @@
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
+
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
index 3c36eb52e968..d7351a17d3e8 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
@@ -72,6 +72,17 @@
#clock-cells = <0>;
clock-frequency = <27000000>;
};
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -122,6 +133,12 @@
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
+
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts
b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 3542844e6977..4ec8a400494e 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -134,6 +134,18 @@
#clock-cells = <0>;
clock-frequency = <27000000>;
};
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&dcc {
@@ -607,3 +619,9 @@
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};
+
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 955810ae7178..7fa77b59906e 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -151,6 +151,18 @@
#clock-cells = <0>;
clock-frequency = <114285000>;
};
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&can1 {
@@ -1082,3 +1094,9 @@
phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
};
+
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts
b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 64d822255ec5..135bfa080828 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -60,6 +60,18 @@
#clock-cells = <0>;
clock-frequency = <27000000>;
};
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&can1 {
@@ -545,3 +557,9 @@
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};
+
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts
b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 3e883d717c2f..20d17a07e7eb 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -65,6 +65,18 @@
#clock-cells = <0>;
clock-frequency = <27000000>;
};
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&can1 {
@@ -557,3 +569,9 @@
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};
+
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts
b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 3a1580dfc400..cfb4f6487675 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -129,6 +129,18 @@
#clock-cells = <0>;
clock-frequency = <48000000>;
};
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&dcc {
@@ -882,3 +894,9 @@
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};
+
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
--
2.43.0
