Signed-off-by: Bhimeswararao Matsa <bhimeswararao.ma...@gmail.com>
---
drivers/i2c/davinci_i2c.c | 118 +++++++++++++++++++-------------------
1 file changed, 59 insertions(+), 59 deletions(-)
diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c
index ffd0dd0b282..caf5fbcc346 100644
--- a/drivers/i2c/davinci_i2c.c
+++ b/drivers/i2c/davinci_i2c.c
@@ -41,20 +41,20 @@ static int _wait_for_bus(struct i2c_regs *i2c_base)
{
int stat, timeout;
- REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&i2c_base->i2c_stat) = 0xffff;
for (timeout = 0; timeout < 10; timeout++) {
- stat = REG(&(i2c_base->i2c_stat));
+ stat = REG(&i2c_base->i2c_stat);
if (!((stat) & I2C_STAT_BB)) {
- REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&i2c_base->i2c_stat) = 0xffff;
return 0;
}
- REG(&(i2c_base->i2c_stat)) = stat;
+ REG(&i2c_base->i2c_stat) = stat;
mdelay(50);
}
- REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&i2c_base->i2c_stat) = 0xffff;
return 1;
}
@@ -64,23 +64,23 @@ static int _poll_i2c_irq(struct i2c_regs *i2c_base, int
mask)
for (timeout = 0; timeout < 10; timeout++) {
mdelay(1);
- stat = REG(&(i2c_base->i2c_stat));
+ stat = REG(&i2c_base->i2c_stat);
if (stat & mask)
return stat;
}
- REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&i2c_base->i2c_stat) = 0xffff;
return stat | I2C_TIMEOUT;
}
static void _flush_rx(struct i2c_regs *i2c_base)
{
while (1) {
- if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
+ if (!(REG(&i2c_base->i2c_stat) & I2C_STAT_RRDY))
break;
- REG(&(i2c_base->i2c_drr));
- REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
+ REG(&i2c_base->i2c_drr);
+ REG(&i2c_base->i2c_stat) = I2C_STAT_RRDY;
mdelay(1);
}
}
@@ -93,9 +93,9 @@ static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
psc = 2;
/* SCLL + SCLH */
div = (CFG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
- REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
- REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
- REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
+ REG(&i2c_base->i2c_psc) = psc; /* 27MHz / (2 + 1) = 9MHz */
+ REG(&i2c_base->i2c_scll) = (div * 50) / 100; /* 50% Duty */
+ REG(&i2c_base->i2c_sclh) = div - REG(&i2c_base->i2c_scll);
return 0;
}
@@ -103,22 +103,22 @@ static uint _davinci_i2c_setspeed(struct i2c_regs
*i2c_base,
static void _davinci_i2c_init(struct i2c_regs *i2c_base,
uint speed, int slaveadd)
{
- if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
- REG(&(i2c_base->i2c_con)) = 0;
+ if (REG(&i2c_base->i2c_con) & I2C_CON_EN) {
+ REG(&i2c_base->i2c_con) = 0;
mdelay(50);
}
_davinci_i2c_setspeed(i2c_base, speed);
- REG(&(i2c_base->i2c_oa)) = slaveadd;
- REG(&(i2c_base->i2c_cnt)) = 0;
+ REG(&i2c_base->i2c_oa) = slaveadd;
+ REG(&i2c_base->i2c_cnt) = 0;
/* Interrupts must be enabled or I2C module won't work */
- REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
+ REG(&i2c_base->i2c_ie) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
/* Now enable I2C controller (get it out of reset) */
- REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
+ REG(&i2c_base->i2c_con) = I2C_CON_EN;
mdelay(1);
}
@@ -140,9 +140,9 @@ static int _davinci_i2c_read(struct i2c_regs *i2c_base, u8
chip,
if (alen != 0) {
/* Start address phase */
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
- REG(&(i2c_base->i2c_cnt)) = alen;
- REG(&(i2c_base->i2c_sa)) = chip;
- REG(&(i2c_base->i2c_con)) = tmp;
+ REG(&i2c_base->i2c_cnt) = alen;
+ REG(&i2c_base->i2c_sa) = chip;
+ REG(&i2c_base->i2c_con) = tmp;
tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
@@ -152,9 +152,9 @@ static int _davinci_i2c_read(struct i2c_regs *i2c_base, u8
chip,
case 2:
/* Send address MSByte */
if (tmp & I2C_STAT_XRDY) {
- REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
+ REG(&i2c_base->i2c_dxr) = (addr >> 8) & 0xff;
} else {
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 1;
}
@@ -166,9 +166,9 @@ static int _davinci_i2c_read(struct i2c_regs *i2c_base, u8
chip,
case 1:
/* Send address LSByte */
if (tmp & I2C_STAT_XRDY) {
- REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
+ REG(&i2c_base->i2c_dxr) = addr & 0xff;
} else {
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 1;
}
@@ -178,7 +178,7 @@ static int _davinci_i2c_read(struct i2c_regs *i2c_base, u8
chip,
CHECK_NACK();
if (!(tmp & I2C_STAT_ARDY)) {
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 1;
}
}
@@ -186,9 +186,9 @@ static int _davinci_i2c_read(struct i2c_regs *i2c_base, u8
chip,
/* Address phase is over, now read 'len' bytes and stop */
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
- REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
- REG(&(i2c_base->i2c_sa)) = chip;
- REG(&(i2c_base->i2c_con)) = tmp;
+ REG(&i2c_base->i2c_cnt) = len & 0xffff;
+ REG(&i2c_base->i2c_sa) = chip;
+ REG(&i2c_base->i2c_con) = tmp;
for (i = 0; i < len; i++) {
tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY | I2C_STAT_NACK |
@@ -197,9 +197,9 @@ static int _davinci_i2c_read(struct i2c_regs *i2c_base, u8
chip,
CHECK_NACK();
if (tmp & I2C_STAT_RRDY) {
- buf[i] = REG(&(i2c_base->i2c_drr));
+ buf[i] = REG(&i2c_base->i2c_drr);
} else {
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 1;
}
}
@@ -209,14 +209,14 @@ static int _davinci_i2c_read(struct i2c_regs *i2c_base,
u8 chip,
CHECK_NACK();
if (!(tmp & I2C_STAT_SCD)) {
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 1;
}
_flush_rx(i2c_base);
- REG(&(i2c_base->i2c_stat)) = 0xffff;
- REG(&(i2c_base->i2c_cnt)) = 0;
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_stat) = 0xffff;
+ REG(&i2c_base->i2c_cnt) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 0;
}
@@ -242,10 +242,10 @@ static int _davinci_i2c_write(struct i2c_regs *i2c_base,
u8 chip,
/* Start address phase */
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
I2C_CON_TRX | I2C_CON_STP;
- REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
+ REG(&i2c_base->i2c_cnt) = (alen == 0) ?
len & 0xffff : (len & 0xffff) + alen;
- REG(&(i2c_base->i2c_sa)) = chip;
- REG(&(i2c_base->i2c_con)) = tmp;
+ REG(&i2c_base->i2c_sa) = chip;
+ REG(&i2c_base->i2c_con) = tmp;
switch (alen) {
case 2:
@@ -255,9 +255,9 @@ static int _davinci_i2c_write(struct i2c_regs *i2c_base, u8
chip,
CHECK_NACK();
if (tmp & I2C_STAT_XRDY) {
- REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
+ REG(&i2c_base->i2c_dxr) = (addr >> 8) & 0xff;
} else {
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 1;
}
/* No break, fall through */
@@ -268,9 +268,9 @@ static int _davinci_i2c_write(struct i2c_regs *i2c_base, u8
chip,
CHECK_NACK();
if (tmp & I2C_STAT_XRDY) {
- REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
+ REG(&i2c_base->i2c_dxr) = addr & 0xff;
} else {
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 1;
}
}
@@ -281,7 +281,7 @@ static int _davinci_i2c_write(struct i2c_regs *i2c_base, u8
chip,
CHECK_NACK();
if (tmp & I2C_STAT_XRDY)
- REG(&(i2c_base->i2c_dxr)) = buf[i];
+ REG(&i2c_base->i2c_dxr) = buf[i];
else
return 1;
}
@@ -291,14 +291,14 @@ static int _davinci_i2c_write(struct i2c_regs *i2c_base,
u8 chip,
CHECK_NACK();
if (!(tmp & I2C_STAT_SCD)) {
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 1;
}
_flush_rx(i2c_base);
- REG(&(i2c_base->i2c_stat)) = 0xffff;
- REG(&(i2c_base->i2c_cnt)) = 0;
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_stat) = 0xffff;
+ REG(&i2c_base->i2c_cnt) = 0;
+ REG(&i2c_base->i2c_con) = 0;
return 0;
}
@@ -307,35 +307,35 @@ static int _davinci_i2c_probe_chip(struct i2c_regs
*i2c_base, u8 chip)
{
int rc = 1;
- if (chip == REG(&(i2c_base->i2c_oa)))
+ if (chip == REG(&i2c_base->i2c_oa))
return rc;
- REG(&(i2c_base->i2c_con)) = 0;
+ REG(&i2c_base->i2c_con) = 0;
if (_wait_for_bus(i2c_base))
return 1;
/* try to read one byte from current (or only) address */
- REG(&(i2c_base->i2c_cnt)) = 1;
- REG(&(i2c_base->i2c_sa)) = chip;
- REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+ REG(&i2c_base->i2c_cnt) = 1;
+ REG(&i2c_base->i2c_sa) = chip;
+ REG(&i2c_base->i2c_con) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
I2C_CON_STP);
mdelay(50);
- if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
+ if (!(REG(&i2c_base->i2c_stat) & I2C_STAT_NACK)) {
rc = 0;
_flush_rx(i2c_base);
- REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&i2c_base->i2c_stat) = 0xffff;
} else {
- REG(&(i2c_base->i2c_stat)) = 0xffff;
- REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
+ REG(&i2c_base->i2c_stat) = 0xffff;
+ REG(&i2c_base->i2c_con) |= I2C_CON_STP;
mdelay(20);
if (_wait_for_bus(i2c_base))
return 1;
}
_flush_rx(i2c_base);
- REG(&(i2c_base->i2c_stat)) = 0xffff;
- REG(&(i2c_base->i2c_cnt)) = 0;
+ REG(&i2c_base->i2c_stat) = 0xffff;
+ REG(&i2c_base->i2c_cnt) = 0;
return rc;
}
--
2.43.0
