> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapa...@altera.com>
> Sent: Tuesday, August 19, 2025 12:18 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> <tien.fong.c...@altera.com>; Tom Rini <tr...@konsulko.com>; Ravulapalli,
> Naresh Kumar <naresh.kumar.ravulapa...@altera.com>
> Subject: [PATCH] arch: arm: dts: stratix10: Add NAND IP to base dtsi
>
> Add NAND node to the base stratix10 dtsi file.
>
> Signed-off-by: Naresh Kumar Ravulapalli
> <nareshkumar.ravulapa...@altera.com>
> ---
> arch/arm/dts/socfpga_stratix10.dtsi | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
> b/arch/arm/dts/socfpga_stratix10.dtsi
> index eb82d663204..750b43d30c0 100644
> --- a/arch/arm/dts/socfpga_stratix10.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> @@ -1,6 +1,7 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2018 Intel Corporation
> + * Copyright (C) 2025 Altera Corporation <www.altera.com>
> */
>
> /dts-v1/;
> @@ -232,6 +233,18 @@
> status = "disabled";
> };
>
> + nand: nand@ffb90000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "altr,socfpga-denali-nand";
> + reg = <0xffb90000 0x10000>,
> + <0xffb80000 0x1000>;
> + reg-names = "nand_data", "denali_reg";
> + interrupts = <0 97 4>;
> + resets = <&rst NAND_RESET>, <&rst
> NAND_OCP_RESET>;
> + status = "disabled";
> + };
> +
> ocram: sram@ffe00000 {
> compatible = "mmio-sram";
> reg = <0xffe00000 0x100000>;
> --
> 2.35.3
Reviewed-by: Tien Fong Chee <tien.fong.c...@altera.com>
Best regards,
Tien Fong
