[PATCH] mips: mtmips: add CPU reset support for MT7628

[Shiji Yang]

Allow the system to reset the CPU without calling the reset
controller. This patch also removed the default SYSRESET controller
for MT7628, as it is now optional.

Signed-off-by: Shiji Yang <yangshij...@outlook.com>
---
 arch/mips/mach-mtmips/Kconfig         | 3 ---
 arch/mips/mach-mtmips/mt7628/init.c   | 8 ++++++++
 arch/mips/mach-mtmips/mt7628/mt7628.h | 1 +
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig
index 3fcd0b8465b..337d2259fa1 100644
--- a/arch/mips/mach-mtmips/Kconfig
+++ b/arch/mips/mach-mtmips/Kconfig
@@ -102,8 +102,6 @@ config SOC_MT7628
        select SYS_MIPS_CACHE_INIT_RAM_LOAD
        select PINCTRL_MT7628
        select MTK_SERIAL
-       select SYSRESET
-       select SYSRESET_RESETCTL
        select SPL_SEPARATE_BSS if SPL
        select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
        select SPL_LOADER_SUPPORT if SPL
@@ -111,7 +109,6 @@ config SOC_MT7628
        select SPL_SIMPLE_BUS if SPL_DM
        select SPL_DM_SERIAL if SPL_DM
        select SPL_CLK if SPL_DM && SPL_SERIAL
-       select SPL_SYSRESET if SPL_DM
        select SPL_OF_LIBFDT if SPL_OF_CONTROL
        help
          This supports MediaTek MT7628/MT7688.
diff --git a/arch/mips/mach-mtmips/mt7628/init.c 
b/arch/mips/mach-mtmips/mt7628/init.c
index 2996fd9ef4e..a0e731121c9 100644
--- a/arch/mips/mach-mtmips/mt7628/init.c
+++ b/arch/mips/mach-mtmips/mt7628/init.c
@@ -110,3 +110,11 @@ ulong notrace get_tbclk(void)
 {
        return gd->arch.timer_freq;
 }
+
+void _machine_restart(void)
+{
+       void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
+
+       while (1)
+               writel(SYS_RST, sysc + SYSCTL_RSTCTL_REG);
+}
diff --git a/arch/mips/mach-mtmips/mt7628/mt7628.h 
b/arch/mips/mach-mtmips/mt7628/mt7628.h
index 391880b014e..aac6e1278b2 100644
--- a/arch/mips/mach-mtmips/mt7628/mt7628.h
+++ b/arch/mips/mach-mtmips/mt7628/mt7628.h
@@ -49,6 +49,7 @@
 
 #define SYSCTL_RSTCTL_REG              0x34
 #define MC_RST                         0x400
+#define SYS_RST                                0x01
 
 #define SYSCTL_AGPIO_CFG_REG           0x3c
 #define EPHY_GPIO_AIO_EN_S             17
-- 
2.50.0