From: Magnus Damm <d...@opensource.se>
Add SCIF support for RZ/A2 r7s9210 including a work around to prevent
the driver from hanging on boot due to TEND flag handling.
Signed-off-by: Magnus Damm <d...@opensource.se>
---
drivers/serial/serial_sh.c | 15 +++++++++++++--
drivers/serial/serial_sh.h | 15 +++++++++++++++
2 files changed, 28 insertions(+), 2 deletions(-)
--- 0001/drivers/serial/serial_sh.c
+++ work/drivers/serial/serial_sh.c 2025-07-01 00:29:33.340877501 +0900
@@ -55,10 +55,21 @@ static void sh_serial_init_generic(struc
sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
sci_in(port, SCFCR);
sci_out(port, SCFCR, 0);
-#if defined(CONFIG_RZA1)
+#if defined(CONFIG_RZA1) || defined(CONFIG_RZA2)
sci_out(port, SCSPTR, 0x0003);
#endif
-
+#if defined(CONFIG_RZA2)
+ /* For SCIF on RZ/A2, the default value of TEND after reset is 0,
+ * however this driver expects it to be 1, so without this workaround
+ * we will get stuck waiting and never send out the first character.
+ * To rememdy the situation, send a character with loopback enabled.
+ */
+ sci_out(port, SCFCR, 1); /* enable loopback */
+ sci_out(port, SCxTDR, 'Z'); /* TX data */
+ mdelay(10);
+ sci_out(port, SCFCR, 6); /* assert FIFO reset to clear RX data */
+ sci_out(port, SCFCR, 0); /* deassert FIFO reset, disable loopback */
+#endif
#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_GEN3) ||
IS_ENABLED(CONFIG_RCAR_GEN4)
if (port->type == PORT_HSCIF)
sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8);
--- 0001/drivers/serial/serial_sh.h
+++ work/drivers/serial/serial_sh.h 2025-07-01 00:26:47.080924446 +0900
@@ -98,6 +98,9 @@ struct uart_port {
# endif
# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
+#elif defined(CONFIG_RZA2)
+# define SCIF_ORER 0x0001 /* Overrun error bit */
+# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0 */
#else
# error CPU subtype not defined
#endif
@@ -390,6 +393,18 @@ SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
#else
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
+#elif defined(CONFIG_RZA2)
+SCIF_FNS(SCSMR, 0x00, 8, 0x00, 16)
+SCIF_FNS(SCBRR, 0x01, 8, 0x02, 8)
+SCIF_FNS(SCSCR, 0x02, 8, 0x04, 16)
+SCIF_FNS(SCxTDR, 0x03, 8, 0x06, 8)
+SCIF_FNS(SCxSR, 0x04, 8, 0x08, 16)
+SCIF_FNS(SCxRDR, 0x05, 8, 0x0A, 8)
+SCIF_FNS(SCFCR, 0, 0, 0x0C, 16)
+SCIF_FNS(SCFDR, 0, 0, 0x0E, 16)
+SCIF_FNS(SCSPTR, 0, 0, 0x10, 16)
+SCIF_FNS(SCLSR, 0, 0, 0x12, 16)
+SCIF_FNS(DL, 0, 0, 0x00, 0) /* dummy */
#elif defined(CONFIG_RZG2L)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x02, 8)
