From: Chao-ying Fu <c...@mips.com>
Add basic support for the MIPS GIC syscon used on the P8700 SoC.
Enables access to interrupt control via device tree matching.
Signed-off-by: Chao-ying Fu <c...@mips.com>
Signed-off-by: Uros Stajic <uros.sta...@htecgroup.com>
---
arch/riscv/Kconfig | 11 +++++++
arch/riscv/cpu/p8700/Kconfig | 2 +-
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/mips_gic.c | 47 +++++++++++++++++++++++++++++
board/mips/boston-riscv/MAINTAINERS | 1 +
5 files changed, 61 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/lib/mips_gic.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b05e0622908..aada4f4061e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -385,6 +385,17 @@ config SIFIVE_CACHE
help
This enables the operations to configure SiFive cache
+config MIPS_GIC
+ bool
+ depends on RISCV_MMODE || SPL_RISCV_MMODE
+ select REGMAP
+ select SYSCON
+ select SPL_REGMAP if SPL
+ select SPL_SYSCON if SPL
+ help
+ The MIPS GIC block holds memory-mapped control and status registers
+ associated with software and timer interrupts.
+
config ANDES_PLICSW
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
diff --git a/arch/riscv/cpu/p8700/Kconfig b/arch/riscv/cpu/p8700/Kconfig
index 0e5e4c9eda6..223130d5443 100644
--- a/arch/riscv/cpu/p8700/Kconfig
+++ b/arch/riscv/cpu/p8700/Kconfig
@@ -8,7 +8,7 @@ config P8700_RISCV
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
- imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply MIPS_GIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply CMD_CPU
imply SPL_CPU_SUPPORT
imply SPL_OPENSBI
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index db8d235c699..692b56cc3f0 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SYS_CACHE_THEAD_CMO) += thead_cmo.o
ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y)
obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o
obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
+obj-$(CONFIG_MIPS_GIC) += mips_gic.o
else
obj-$(CONFIG_SBI) += sbi.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/mips_gic.c b/arch/riscv/lib/mips_gic.c
new file mode 100644
index 00000000000..7d761c58e74
--- /dev/null
+++ b/arch/riscv/lib/mips_gic.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Chao-ying Fu <c...@mips.com>
+ *
+ * U-Boot syscon driver for MIPS GIC.
+ */
+
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int riscv_init_ipi(void)
+{
+ return 0;
+}
+
+int riscv_send_ipi(int hart)
+{
+ return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+ return 0;
+}
+
+int riscv_get_ipi(int hart, int *pending)
+{
+ return 0;
+}
+
+static const struct udevice_id mips_gic_ids[] = {
+ { .compatible = "mips,gic0", .data = RISCV_SYSCON_PLICSW },
+ { }
+};
+
+U_BOOT_DRIVER(mips_gic) = {
+ .name = "mips_gic",
+ .id = UCLASS_SYSCON,
+ .of_match = mips_gic_ids,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/board/mips/boston-riscv/MAINTAINERS
b/board/mips/boston-riscv/MAINTAINERS
index bc59a628c79..0d9a951441f 100644
--- a/board/mips/boston-riscv/MAINTAINERS
+++ b/board/mips/boston-riscv/MAINTAINERS
@@ -8,3 +8,4 @@ F: arch/riscv/include/asm/arch-p8700/
F: configs/boston-p8700_defconfig
F: arch/riscv/dts/boston-p8700.dts
F: drivers/gpio/eg20t-gpio.c
+F: arch/riscv/lib/mips_gic.c
--
2.34.1
