[PATCH v3 4/5] clk/qcom: sc7280: add uart7 clocks

[Casey Connolly]

Allow us to power up UART7 so we can load the QUP firmware, this is used
for bluetooth on RB3 Gen 2 and possibly other boards.

Signed-off-by: Casey Connolly <casey.conno...@linaro.org>
---
 drivers/clk/qcom/clock-sc7280.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 
bf3c6c4ae647a46f7f96b10c0e3ed76a2f2ebee1..55a233df39450e511aebf7892214967c284a603e
 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -67,8 +67,13 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)
                freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s2_clk_src, rate);
                clk_rcg_set_rate_mnd(priv->base, 0x17600,
                                     freq->pre_div, freq->m, freq->n, 
freq->src, 16);
                return freq->freq;
+       case GCC_QUPV3_WRAP0_S7_CLK: /* UART7 */
+               freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s2_clk_src, rate);
+               clk_rcg_set_rate_mnd(priv->base, 0x17860,
+                                    freq->pre_div, freq->m, freq->n, 
freq->src, 16);
+               return freq->freq;
        case GCC_USB30_PRIM_MASTER_CLK:
                freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
                clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
                                     freq->pre_div, freq->m, freq->n, 
freq->src, 8);
@@ -128,8 +133,9 @@ static const struct gate_clk sc7280_clks[] = {
        GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
        GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
        GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
        GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x52008, BIT(15)),
+       GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x52008, BIT(17)),
        GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
        GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),
        GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),
        GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)),

-- 
2.49.0