On Thu, Jun 12, 2025 at 01:50:15PM +0200, Heiko Thiery wrote:
> This is same as done in 27cd65ca1bf1 ("mach-k3: am62ax: enable caches for the
> SPL stage").
>
> This is resulting in ~2x speedup in the A53 SPL stage.
>
> Signed-off-by: Heiko Thiery <heiko.thi...@gmail.com>
> ---
> arch/arm/mach-k3/j722s/j722s_init.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-k3/j722s/j722s_init.c
> b/arch/arm/mach-k3/j722s/j722s_init.c
> index af211377e7c..591aa1d60d5 100644
> --- a/arch/arm/mach-k3/j722s/j722s_init.c
> +++ b/arch/arm/mach-k3/j722s/j722s_init.c
> @@ -162,6 +162,8 @@ static void k3_mem_init(void)
> if (ret)
> panic("DRAM init failed: %d\n", ret);
> }
> +
> + spl_enable_cache();
> }
>
> static __maybe_unused void enable_mcu_esm_reset(void)A bit less a comment for you and more a comment for all the TI folks, can't we re-architect this a bit to be common? I think I even made that point on another patch doing this same thing for another K3 part. -- Tom
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