Hi,
> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapa...@altera.com>
> Sent: Tuesday, June 3, 2025 7:55 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> <tien.fong.c...@altera.com>; Tom Rini <tr...@konsulko.com>; Ravulapalli,
> Naresh Kumar <naresh.kumar.ravulapa...@altera.com>
> Subject: [PATCH v3 4/7] drivers: ddr: altera: Clean common code for SoC32
> devices
>
> Move common code sdram_init_ecc_bits() to new common SoC32 file.
> Preparation for next gen devices which uses the same ECC init function.
>
> Signed-off-by: Naresh Kumar Ravulapalli
> <nareshkumar.ravulapa...@altera.com>
> ---
> drivers/ddr/altera/Makefile | 2 +-
> drivers/ddr/altera/sdram_arria10.c | 19 +-----------------
> drivers/ddr/altera/sdram_soc32.c | 31
> ++++++++++++++++++++++++++++++
> drivers/ddr/altera/sdram_soc32.h | 11 +++++++++++
> 4 files changed, 44 insertions(+), 19 deletions(-) create mode 100644
> drivers/ddr/altera/sdram_soc32.c create mode 100644
> drivers/ddr/altera/sdram_soc32.h
>
> diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index
> c627f16711e..78b0afc38e7 100644
> --- a/drivers/ddr/altera/Makefile
> +++ b/drivers/ddr/altera/Makefile
> @@ -8,7 +8,7 @@
>
> ifdef CONFIG_$(PHASE_)ALTERA_SDRAM
> obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
> -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_soc32.o
> sdram_arria10.o
> obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o
> sdram_s10.o
> obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o
> sdram_agilex.o
> obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
> diff --git a/drivers/ddr/altera/sdram_arria10.c
> b/drivers/ddr/altera/sdram_arria10.c
> index ba6f0f4160f..4c48b1bab6d 100644
> --- a/drivers/ddr/altera/sdram_arria10.c
> +++ b/drivers/ddr/altera/sdram_arria10.c
> @@ -23,6 +23,7 @@
> #include <linux/delay.h>
> #include <linux/kernel.h>
> #include <hang.h>
> +#include "sdram_soc32.h"
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -194,24 +195,6 @@ static int sdram_is_ecc_enabled(void)
> ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
> }
>
> -/* Initialize SDRAM ECC bits to avoid false DBE */ -static void
> sdram_init_ecc_bits(u32 size) -{
> - icache_enable();
> -
> - memset(0, 0, 0x8000);
> - gd->arch.tlb_addr = 0x4000;
> - gd->arch.tlb_size = PGTABLE_SIZE;
> -
> - dcache_enable();
> -
> - printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
> - memset((void *)0x8000, 0, size - 0x8000);
> - flush_dcache_all();
> - printf("DDRCAL: Scrubbing ECC RAM done.\n");
> - dcache_disable();
> -}
> -
> /* Function to startup the SDRAM*/
> static int sdram_startup(void)
> {
> diff --git a/drivers/ddr/altera/sdram_soc32.c
> b/drivers/ddr/altera/sdram_soc32.c
> new file mode 100644
> index 00000000000..0b928a2352f
> --- /dev/null
> +++ b/drivers/ddr/altera/sdram_soc32.c
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */
Move to new line below
> +
> + #include <cpu_func.h>
> +#include <asm/system.h>
> +#include <linux/sizes.h>
> +#include "sdram_soc32.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define PGTABLE_OFF 0x4000
> +
> +/* Initialize SDRAM ECC bits to avoid false DBE */ void
> +sdram_init_ecc_bits(u32 size) {
> + icache_enable();
> +
> + memset(0, 0, 0x8000);
> + gd->arch.tlb_addr = 0x4000;
> + gd->arch.tlb_size = PGTABLE_SIZE;
> +
> + dcache_enable();
> +
> + printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
> + memset((void *)0x8000, 0, size - 0x8000);
> + flush_dcache_all();
> + printf("DDRCAL: Scrubbing ECC RAM done.\n");
> + dcache_disable();
> +}
> diff --git a/drivers/ddr/altera/sdram_soc32.h
> b/drivers/ddr/altera/sdram_soc32.h
> new file mode 100644
> index 00000000000..4c6137e728d
> --- /dev/null
> +++ b/drivers/ddr/altera/sdram_soc32.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */
Move to new line below
> +
> +#ifndef _SDRAM_SOC32_H_
> +#define _SDRAM_SOC32_H_
> +
> +void sdram_init_ecc_bits(u32 size);
> +
> +#endif /* _SDRAM_SOC32_H_ */
> --
> 2.35.3
BR,
Tien Fong
