Re: [PATCH 03/10] ARM: stm32: Limit early cache enablement in SPL to STM32MP15xx

[Patrick DELAUNAY]

On 5/12/25 19:21, Marek Vasut wrote:

The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.

Signed-off-by: Marek Vasut <marek.va...@mailbox.org>
---
Cc: Cheick Traore <cheick.tra...@foss.st.com>
Cc: Fabrice Gasnier <fabrice.gasn...@foss.st.com>
Cc: Gatien Chevallier <gatien.chevall...@foss.st.com>
Cc: Lionel Debieve <lionel.debi...@foss.st.com>
Cc: Pascal Zimmermann <pzimmerm...@dh-electronics.com>
Cc: Patrice Chotard <patrice.chot...@foss.st.com>
Cc: Patrick Delaunay <patrick.delau...@foss.st.com>
Cc: Simon Glass <s...@chromium.org>
Cc: Sughosh Ganu <sughosh.g...@linaro.org>
Cc: Tom Rini <tr...@konsulko.com>
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  arch/arm/mach-stm32mp/stm32mp1/cpu.c | 9 ++++++---
  arch/arm/mach-stm32mp/stm32mp1/spl.c | 3 ++-
  2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c 
b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index 9ab5a3ede52..1ae82489a4b 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -28,7 +28,9 @@
   * early TLB into the .data section so that it not get cleared
   * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
   */
+#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X))
  u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
+#endif

u32 get_bootmode(void)

  {
@@ -95,18 +97,19 @@ void dram_bank_mmu_setup(int bank)
   */
  static void early_enable_caches(void)
  {
+#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X))

can you replace #if, if it possible?


if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X))

        return;

        /* I-cache is already enabled in start.S: cpu_init_cp15 */
-
        if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
                return;

#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))

-               gd->arch.tlb_size = PGTABLE_SIZE;
-               gd->arch.tlb_addr = (unsigned long)&early_tlb;
+       gd->arch.tlb_size = PGTABLE_SIZE;
+       gd->arch.tlb_addr = (unsigned long)&early_tlb;
  #endif

/* enable MMU (default configuration) */

        dcache_enable();
+#endif
  }

/*

diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c 
b/arch/arm/mach-stm32mp/stm32mp1/spl.c
index 9c4fafbf478..e63bdaaf42f 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/spl.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c
@@ -220,10 +220,11 @@ void board_init_f(ulong dummy)
         * activate cache on DDR only when DDR is fully initialized
         * to avoid speculative access and issue in get_ram_size()
         */
-       if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+       if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && 
!IS_ENABLED(CONFIG_STM32MP13X)) {
                mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
                                                CONFIG_DDR_CACHEABLE_SIZE,
                                                DCACHE_DEFAULT_OPTION);
+       }
  }

void spl_board_prepare_for_boot(void)