Hi Shmuel,
Thank you for the patch and for contributing to U-Boot.
On ven., mai 09, 2025 at 01:23, Shmuel Melamud <smela...@redhat.com> wrote:
> Add support of Renesas R-Car Gen4 watchdog timer. Timeouts up to
> 8184.0s are supported (CKS1 register is not involved). The watchdog
> uses the clock type CLK_TYPE_GEN4_MDSEL, so handling of this constant
> is added to gen3_clk_get_rate64() function.
>
> Signed-off-by: Shmuel Leib Melamud <smela...@redhat.com>
> ---
> drivers/clk/renesas/clk-rcar-gen3.c | 4 +-
> drivers/watchdog/Kconfig | 8 ++
> drivers/watchdog/Makefile | 1 +
> drivers/watchdog/renesas_wdt.c | 172 ++++++++++++++++++++++++++++
> 4 files changed, 184 insertions(+), 1 deletion(-)
> create mode 100644 drivers/watchdog/renesas_wdt.c
I've tried to apply this with b4 but it seems to complain about
whitespace corruption:
$ b4 shazam -s -l --check
camfvly31c0yptgpkx3ze1kmjn_hpqcjh-ghbc+jamplmdcs...@mail.gmail.com
✓ [PATCH] renesas: Renesas R-Car Gen4 watchdog driver
+ Link:
https://lore.kernel.org/r/camfvly31c0yptgpkx3ze1kmjn_hpqcjh-ghbc+jamplmdcs...@mail.gmail.com
+ Signed-off-by: Mattijs Korpershoek <mkorpersh...@kernel.org>
● checkpatch.pl: 121: ERROR: patch seems to be corrupt (line wrapped?)
[...] (lots of more whitespace errors.)
Can you please double check that the patch has been formatted properly
when sending?
See: https://docs.u-boot.org/en/latest/develop/sending_patches.html
Thanks,
Mattijs
>
> diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
> b/drivers/clk/renesas/clk-rcar-gen3.c
> index 375cc4a4930..5745acf4023 100644
> --- a/drivers/clk/renesas/clk-rcar-gen3.c
> +++ b/drivers/clk/renesas/clk-rcar-gen3.c
> @@ -68,7 +68,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv
> *priv, struct clk *clk,
> if (ret)
> return ret;
>
> - if (core->type == CLK_TYPE_GEN3_MDSEL) {
> + if (core->type == CLK_TYPE_GEN3_MDSEL || core->type ==
> CLK_TYPE_GEN4_MDSEL) {
> shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
> parent->dev = clk->dev;
> parent->id = core->parent >> shift;
> @@ -318,6 +318,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
> "FIXED");
>
> case CLK_TYPE_GEN3_MDSEL:
> + fallthrough;
> + case CLK_TYPE_GEN4_MDSEL:
> shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
> div = (core->div >> shift) & 0xffff;
> rate = gen3_clk_get_rate64(&parent) / div;
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 1bb67f50352..a0f2948335f 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -335,6 +335,14 @@ config WDT_K3_RTI_FW_FILE
>
> endif
>
> +config WDT_RENESAS
> + bool "Renesas watchdog timer support"
> + depends on WDT && R8A779F0
> + select CLK
> + select CLK_RENESAS
> + help
> + Enables Renesas SoC R8A779F0 watchdog timer support.
> +
> config WDT_SANDBOX
> bool "Enable Watchdog Timer support for Sandbox"
> depends on SANDBOX && WDT
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index e6bd4c587af..c4467d6e126 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
> obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o
> obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
> obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
> +obj-$(CONFIG_WDT_RENESAS) += renesas_wdt.o
> obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
> obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
> obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o
> diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
> new file mode 100644
> index 00000000000..97550794a2e
> --- /dev/null
> +++ b/drivers/watchdog/renesas_wdt.c
> @@ -0,0 +1,172 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +// Copyright 2025 Red Hat, Inc., Shmuel Leib Melamud <smela...@redhat.com>
> +
> +#include <clk.h>
> +#include <dm.h>
> +#include <wdt.h>
> +#include <asm/io.h>
> +#include <dm/device_compat.h>
> +#include <linux/delay.h>
> +#include <linux/iopoll.h>
> +
> +#define usleep_range(a, b) udelay((b))
> +
> +struct renesas_wdt {
> + u32 cnt;
> + u32 csra;
> + u32 csrb;
> +};
> +
> +#define RWTCSRA_WOVF BIT(4)
> +#define RWTCSRA_WRFLG BIT(5)
> +#define RWTCSRA_TME BIT(7)
> +
> +#define CSR_MASK 0xA5A5A500
> +#define CNT_MASK 0x5A5A0000
> +
> +/*
> + * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
> + * divider (12 bits). d is only a factor to fully utilize the WDT counter and
> + * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
> + */
> +#define MUL_BY_CLKS_PER_SEC(p, d) \
> + DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
> +
> +/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
> +#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
> +
> +static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
> +
> +struct renesas_wdt_priv {
> + struct renesas_wdt __iomem *wdt;
> + unsigned long clk_rate;
> + u8 cks;
> + struct clk clk;
> +};
> +
> +static void rwdt_wait_cycles(struct renesas_wdt_priv *priv, unsigned
> int cycles)
> +{
> + unsigned int delay;
> +
> + delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
> +
> + usleep_range(delay, 2 * delay);
> +}
> +
> +static int renesas_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
> +{
> + struct renesas_wdt_priv *priv = dev_get_priv(dev);
> + u64 max_timeout;
> + u8 val;
> +
> + max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
> + timeout = min(max_timeout, timeout / 1000);
> +
> + /* Stop the timer before we modify any register */
> + val = readb_relaxed(&priv->wdt->csra) & ~RWTCSRA_TME;
> + writel_relaxed(val | CSR_MASK, &priv->wdt->csra);
> + /* Delay 2 cycles before setting watchdog counter */
> + rwdt_wait_cycles(priv, 2);
> +
> + while (readb_relaxed(&priv->wdt->csra) & RWTCSRA_WRFLG)
> + cpu_relax();
> +
> + writel_relaxed((65536 - MUL_BY_CLKS_PER_SEC(priv, timeout)) | CNT_MASK,
> + &priv->wdt->cnt);
> +
> + writel_relaxed(priv->cks | RWTCSRA_TME | CSR_MASK, &priv->wdt->csra);
> +
> + return 0;
> +}
> +
> +static int renesas_wdt_stop(struct udevice *dev)
> +{
> + struct renesas_wdt_priv *priv = dev_get_priv(dev);
> +
> + writel_relaxed(priv->cks | CSR_MASK, &priv->wdt->csra);
> +
> + return 0;
> +}
> +
> +static int renesas_wdt_reset(struct udevice *dev)
> +{
> + struct renesas_wdt_priv *priv = dev_get_priv(dev);
> + u8 val;
> +
> + /* Stop the timer before we modify any register */
> + val = readb_relaxed(&priv->wdt->csra) & ~RWTCSRA_TME;
> + writel_relaxed(val | CSR_MASK, &priv->wdt->csra);
> + /* Delay 2 cycles before setting watchdog counter */
> + rwdt_wait_cycles(priv, 2);
> +
> + writel_relaxed(0xffff | CNT_MASK, &priv->wdt->cnt);
> + /* smallest divider to reboot soon */
> + writel_relaxed(0 | CSR_MASK, &priv->wdt->csra);
> +
> + readb_poll_timeout(&priv->wdt->csra, val, !(val & RWTCSRA_WRFLG), 100);
> +
> + writel_relaxed(RWTCSRA_TME | CSR_MASK, &priv->wdt->csra);
> +
> + /* wait 2 cycles, so watchdog will trigger */
> + rwdt_wait_cycles(priv, 2);
> +
> + return 0;
> +}
> +
> +static int renesas_wdt_probe(struct udevice *dev)
> +{
> + struct renesas_wdt_priv *priv = dev_get_priv(dev);
> + unsigned long clks_per_sec;
> + int ret, i;
> +
> + priv->wdt = dev_remap_addr(dev);
> + if (!priv->wdt)
> + return -EINVAL;
> +
> + ret = clk_get_by_index(dev, 0, &priv->clk);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_enable(&priv->clk);
> + if (ret)
> + return ret;
> +
> + priv->clk_rate = clk_get_rate(&priv->clk);
> + if (!priv->clk_rate)
> + return -ENOENT;
> +
> + for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
> + clks_per_sec = priv->clk_rate / clk_divs[i];
> + if (clks_per_sec && clks_per_sec < 65536) {
> + priv->cks = i;
> + break;
> + }
> + }
> +
> + /* can't find a suitable clock divider */
> + if (i < 0)
> + return -ERANGE;
> +
> + return 0;
> +}
> +
> +static const struct wdt_ops renesas_wdt_ops = {
> + .start = renesas_wdt_start,
> + .reset = renesas_wdt_reset,
> + .stop = renesas_wdt_stop,
> +};
> +
> +static const struct udevice_id renesas_wdt_ids[] = {
> + { .compatible = "renesas,r8a779f0-wdt" },
> + { .compatible = "renesas,rcar-gen4-wdt" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(wdt_renesas) = {
> + .name = "wdt_renesas",
> + .id = UCLASS_WDT,
> + .of_match = renesas_wdt_ids,
> + .ops = &renesas_wdt_ops,
> + .probe = renesas_wdt_probe,
> + .priv_auto = sizeof(struct renesas_wdt_priv),
> +};
> --
> 2.49.0
