From: Michael Bode <michael.b...@bshg.com>
A small delay between DRAM read access with wrong parameters and
reconfiguration is necessary.
Without a delay between DRAM read access and a following reconfiguration
this reconfiguration fails for certain DRAM chips (Nanya).
Signed-off-by: Michael Bode <michael.b...@bshg.com>
Signed-off-by: Michael Trimarchi <mich...@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binac...@amarulasolutions.com>
---
Changes in v3:
- Drop changes on arch/arm/include/asm/arch-mx6/mx6-ddr.h and
arch/arm/mach-imx/mx6/ddr.c files from patch
[1/1] "board: bsh: imx6ulz_smm_m2: Match SPL DDR settings to DCD
table"
Changes in v2:
- Add 'static struct' globally in the module where the definitions
can mabe static.
- Use standard C comment style
- Remove unnecessary variable initializations
board/bsh/imx6ulz_smm_m2/spl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c
index e8255b6d2a62..c330e4d6d39d 100644
--- a/board/bsh/imx6ulz_smm_m2/spl.c
+++ b/board/bsh/imx6ulz_smm_m2/spl.c
@@ -13,6 +13,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
+#include <linux/delay.h>
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
@@ -65,10 +66,12 @@ static void spl_dram_init(void)
/* Already configured, nothing to do */
break;
case SZ_256M:
+ udelay(1);
ddr_cfg_write(&bsh_dram_timing_256mb);
break;
case SZ_128M:
default:
+ udelay(1);
ddr_cfg_write(&bsh_dram_timing_128mb);
break;
}
--
2.43.0
base-commit: a3e09b24ffd4429909604f1b28455b44306edbaa
branch: bsh-202505-RAM
