Implement get_reset_reason() for AM62x to enable reporting of
the reset cause in the cpuinfo output.
Signed-off-by: Wadim Egorov <w.ego...@phytec.de>
---
arch/arm/mach-k3/am62x/boot.c | 40 +++++++++++++++++++
arch/arm/mach-k3/include/mach/am62_hardware.h | 19 +++++++++
2 files changed, 59 insertions(+)
diff --git a/arch/arm/mach-k3/am62x/boot.c b/arch/arm/mach-k3/am62x/boot.c
index 132b42f7edb..a3a6cda6bdb 100644
--- a/arch/arm/mach-k3/am62x/boot.c
+++ b/arch/arm/mach-k3/am62x/boot.c
@@ -101,3 +101,43 @@ u32 get_boot_device(void)
return bootmedia;
}
+
+const char *get_reset_reason(void)
+{
+ u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC);
+
+ /* After reading reset source register, software must clear it */
+ if (reset_reason)
+ writel(reset_reason, CTRLMMR_MCU_RST_SRC);
+
+ if (reset_reason == 0 ||
+ (reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN |
+ RST_SRC_SW_MAIN_POR_FROM_MCU |
+ RST_SRC_DS_MAIN_PORZ)))
+ return "POR";
+
+ if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR))
+ return "ESM";
+
+ if (reset_reason & RST_SRC_DM_WDT_RST)
+ return "WDOG";
+
+ if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN |
+ RST_SRC_SW_MAIN_WARM_FROM_MCU |
+ RST_SRC_SW_MCU_WARM_RST))
+ return "RST";
+
+ if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST))
+ return "DMSC";
+
+ if (reset_reason & RST_SRC_DEBUG_RST)
+ return "JTAG";
+
+ if (reset_reason & RST_SRC_THERMAL_RST)
+ return "THERMAL";
+
+ if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN))
+ return "PIN";
+
+ return "UNKNOWN";
+}
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h
b/arch/arm/mach-k3/include/mach/am62_hardware.h
index bcbc4821c82..c33362696c4 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -79,6 +79,25 @@
#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
+/* Reset Reason Detection */
+#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178)
+
+#define RST_SRC_SAFETY_ERR BIT(31)
+#define RST_SRC_MAIN_ESM_ERR BIT(30)
+#define RST_SRC_SW_MAIN_POR_FROM_MAIN BIT(25)
+#define RST_SRC_SW_MAIN_POR_FROM_MCU BIT(24)
+#define RST_SRC_DS_MAIN_PORZ BIT(23)
+#define RST_SRC_DM_WDT_RST BIT(22)
+#define RST_SRC_SW_MAIN_WARM_FROM_MAIN BIT(21)
+#define RST_SRC_SW_MAIN_WARM_FROM_MCU BIT(20)
+#define RST_SRC_SW_MCU_WARM_RST BIT(16)
+#define RST_SRC_SMS_WARM_RST BIT(13)
+#define RST_SRC_SMS_COLD_RST BIT(12)
+#define RST_SRC_DEBUG_RST BIT(8)
+#define RST_SRC_THERMAL_RST BIT(4)
+#define RST_SRC_MAIN_RESET_PIN BIT(2)
+#define RST_SRC_MCU_RESET_PIN BIT(0)
+
/* Debounce register configuration */
#define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 +
(index * 4))
--
2.34.1
