[PATCH v4 02/12] video: rockchip: dw_mipi_dsi: Improve pixel clock calculations

[Dang Huynh]

From: Ondrej Jirman <m...@xff.cz>

Calculate burst mode overhead in one place for both internal
and external PHY use case and exit if out of range, instead
of ignoring the wrong value.

Signed-off-by: Ondrej Jirman <m...@xff.cz>
Signed-off-by: Dang Huynh <danc...@riseup.net>
---
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c 
b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index 
fa512173510b1ee6f51e6269eb249e24d0e980f8..c47992dfb133cda029eba82e842ac824ceead64b
 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -526,8 +526,6 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct 
display_timing *timings,
        struct udevice *dev = device->dev;
        struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
        int bpp;
-       unsigned long mpclk, tmp;
-       unsigned int target_mbps = 1000;
        unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
        unsigned long best_freq = 0;
        unsigned long fvco_min, fvco_max, fin, fout;
@@ -544,30 +542,28 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct 
display_timing *timings,
                return bpp;
        }
 
-       mpclk = DIV_ROUND_UP(timings->pixelclock.typ, 1000);
-       if (mpclk) {
-               /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
-               tmp = (mpclk * (bpp / lanes) * 10 / 8) / 1000;
-               if (tmp < max_mbps)
-                       target_mbps = tmp;
-               else
-                       dev_err(dsi->dsi_host,
-                               "DPHY clock frequency is out of range\n");
+       fout = timings->pixelclock.typ / MSEC_PER_SEC * bpp / lanes;
+       if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+               fout = fout * 12 / 10;
+       fout *= MSEC_PER_SEC;
+
+       if (fout > max_mbps * USEC_PER_SEC) {
+               dev_err(dsi->dsi_host, "DPHY clock frequency is out of 
range\n");
+               return -EINVAL;
        }
 
        /* for external phy only the mipi_dphy_config is necessary */
        if (generic_phy_valid(&dsi->phy)) {
-               phy_mipi_dphy_get_default_config(timings->pixelclock.typ  * 10 
/ 8,
+               phy_mipi_dphy_get_default_config(fout / bpp * lanes,
                                                 bpp, lanes,
                                                 &dsi->phy_opts);
-               dsi->lane_mbps = target_mbps;
+               dsi->lane_mbps = DIV_ROUND_UP(fout, USEC_PER_SEC);
                *lane_mbps = dsi->lane_mbps;
 
                return 0;
        }
 
        fin = clk_get_rate(dsi->ref);
-       fout = target_mbps * USEC_PER_SEC;
 
        /* constraint: 5Mhz <= Fref / N <= 40MHz */
        min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);

-- 
2.49.0