Hang has been observed on QEMU, as it starts with indac
read and fills sram, but after dma is triggered, it tries
dac read instead (based on priority) which gets blocked.
Disable the DAC mode in indirect DMA read and enable back
for writes as DAC mode is used.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbar...@amd.com>
---
drivers/spi/cadence_ospi_versal.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/spi/cadence_ospi_versal.c
b/drivers/spi/cadence_ospi_versal.c
index fbeb0c6a85c..a78a282c543 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -36,6 +36,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
bytes_to_dma = n_rx - rx_rem;
if (bytes_to_dma) {
+ if (priv->use_dac_mode)
+ clrbits_le32(priv->regbase + CQSPI_REG_CONFIG,
+ CQSPI_REG_CONFIG_DIRECT);
+
cadence_qspi_apb_enable_linear_mode(false);
reg = readl(priv->regbase + CQSPI_REG_CONFIG);
reg |= CQSPI_REG_CONFIG_ENBL_DMA;
@@ -116,6 +120,9 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
memcpy(rxbuf, rxbuf + 1, n_rx - 1);
}
+ if (priv->use_dac_mode)
+ cadence_qspi_apb_dac_mode_enable(priv->regbase);
+
return 0;
}
--
2.34.1
