On 4/23/25 13:09, E Shattow wrote:
> Quoting Emil reply to
> https://lore.kernel.org/lkml/cajm55z95pwtzmw-wpcuab1bgpvongaryyjunqsfcltnyvmz...@mail.gmail.com/
>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
>> index 8a59c3001339..6bb13af82147 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
>> @@ -635,6 +635,7 @@ GPOEN_DISABLE,
>> };
>>
>> &uart0 {
>> + clock-frequency = <24000000>;
>> pinctrl-names = "default";
>> pinctrl-0 = <&uart0_pins>;
>> status = "okay";
>
> "The uart0 node already has a reference to the uart0_core clock, so it
> shouldn't need this property."
>
> jh7110-common-u-boot.dtsi-26-&uart0 {
> jh7110-common-u-boot.dtsi-27- bootph-pre-ram;
> jh7110-common-u-boot.dtsi-28- reg-offset = <0>;
> jh7110-common-u-boot.dtsi-29- current-speed = <115200>;
> jh7110-common-u-boot.dtsi:30: clock-frequency = <24000000>;
>
> $ grep -B1 -rn 24000000 dts/upstream/src/riscv/starfive/
> dts/upstream/src/riscv/starfive/jh7110-common.dtsi-115-&osc {
> dts/upstream/src/riscv/starfive/jh7110-common.dtsi:116: clock-frequency
> = <24000000>;
>
> What should U-Boot be doing to get this uart0 setting when OF_UPSTREAM ?
>
> -E
P.S. As best I can yet understand in drivers/serial/ns16550.c the call
to clk_get_by_index() returns -19 (error) when in SPL and returns 0
(success) when in U-Boot Main. I've tried adding bootph-pre-ram to
every node in devicetree but it's the same error in SPL phase. Is this
supposed to be working in SPL? -E
