On 4/22/25 10:24, Patrick DELAUNAY wrote:
> Hi
>
> On 4/1/25 15:14, Patrice Chotard wrote:
>> Since upstream kernel commit bda732fda193 ("ARM: dts: stm32: fix
>> DSI peripheral clock on stm32mp15 boards"), DSI clock can't be enabled
>> as shown on following U-Boot log:
>>
>> MMC: STM32 SD/MMC: 0
>> Loading Environment from MMC... Reading from MMC(0)... OK
>> clk id 57 not found
>> stm32-display-dsi dsi@5a000000: peripheral clock enable error -22
>> stm32_display display-controller@5a001000: panel device error -22
>> In: serial
>> Out: serial
>> Err: serial
>> Net: eth0: ethernet@5800a000
>>
>> Update clk-stm32mp1 driver accordingly.
>>
>> Signed-off-by: Patrice Chotard <patrice.chot...@foss.st.com>
>> ---
>>
>> drivers/clk/stm32/clk-stm32mp1.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/stm32/clk-stm32mp1.c
>> b/drivers/clk/stm32/clk-stm32mp1.c
>> index 4044edfb768..204a4b7de45 100644
>> --- a/drivers/clk/stm32/clk-stm32mp1.c
>> +++ b/drivers/clk/stm32/clk-stm32mp1.c
>> @@ -550,7 +550,7 @@ static const struct stm32mp1_clk_gate
>> stm32mp1_clk_gate[] = {
>> STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
>> STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
>> - STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
>> + STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI, _DSI_SEL),
>> STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
>> STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
>> STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
>
>
> See down stream path: "clk: stm32mp1: fix DSI clock setting"
Right, i missed this one.
>
> in fact both clock, DSI_K and DSI are supported, with the other source clock
>
> STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
> STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
> + STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI, _PLL4_P),
> STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
> STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
>
> => just need to add the "DSI" clock with same bit but with "PLL4_P" as source
Thanks
Patrice
>
