> -----Original Message-----
> From: Meng, Tingting <tingting.m...@altera.com>
> Sent: Monday, April 21, 2025 1:14 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Chee, Tien Fong
> <tien.fong.c...@altera.com>; Meng, Tingting <tingting.m...@altera.com>;
> Hea, Kok Kiang <kok.kiang....@altera.com>; Maniyam, Dinesh
> <dinesh.mani...@altera.com>; Ng, Boon Khai <boon.khai...@altera.com>;
> Yuslaimi, Alif Zakuan <alif.zakuan.yusla...@altera.com>; Rosdi, Danish
> Ahmad <danish.ahmad.ro...@altera.com>; Zamri, Muhammad Hazim Izzat
> <muhammad.hazim.izzat.za...@altera.com>; Lim, Jit Loon
> <jit.loon....@altera.com>
> Subject: [PATCH v1 3/5] arm: dts: agilex5: Update CCU configuration
>
> From: Tingting Meng <tingting.m...@altera.com>
>
> Cache allocation for dirty writes in the CCU system cache was disabled for
> performance optimization.
>
> Signed-off-by: Tingting Meng <tingting.m...@altera.com>
> ---
> arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> index 8d6503dd091..dd6cb558f82 100644
> --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
> @@ -208,7 +208,8 @@
> intel,offset-settings =
> /* DMIUSMCTCR */
> <0x00000300 0x00000001
> 0x00000003>,
> - <0x00000300 0x00000003
> 0x00000003>;
> + <0x00000300 0x00000003
> 0x00000003>,
> + <0x00000308 0x00000004
> 0x0000001F>;
> bootph-all;
> };
>
> @@ -218,7 +219,8 @@
> intel,offset-settings =
> /* DMIUSMCTCR */
> <0x00000300 0x00000001
> 0x00000003>,
> - <0x00000300 0x00000003
> 0x00000003>;
> + <0x00000300 0x00000003
> 0x00000003>,
> + <0x00000308 0x00000004
> 0x0000001F>;
> bootph-all;
> };
> };
> --
> 2.25.1
Reviewed-by: Tien Fong Chee <tien.fong.c...@altera.com>
Best regards,
Tien Fong
