Update GMAC speed and flow control fields in GRF_SOC_CON1 to use
RK3288_GMAC_* prefix, ensuring a consistent naming convention. It also
shifts each mask/bit definition to match the actual hardware bits, which
makes future usage easier.
Signed-off-by: Christoph Fritz <chf.fr...@googlemail.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 894d3a40b09..0111b3a0ded 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -934,21 +934,21 @@ enum {
RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT),
RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT),
- GMAC_SPEED_SHIFT = 0xa,
- GMAC_SPEED_MASK = 1,
- GMAC_SPEED_10M = 0,
- GMAC_SPEED_100M,
+ RK3288_GMAC_SPEED_SHIFT = 0xa,
+ RK3288_GMAC_SPEED_MASK = (1 << RK3288_GMAC_SPEED_SHIFT),
+ RK3288_GMAC_SPEED_10M = (0 << RK3288_GMAC_SPEED_SHIFT),
+ RK3288_GMAC_SPEED_100M = (1 << RK3288_GMAC_SPEED_SHIFT),
- GMAC_FLOWCTRL_SHIFT = 0x9,
- GMAC_FLOWCTRL_MASK = 1,
+ RK3288_GMAC_FLOWCTRL_SHIFT = 0x9,
+ RK3288_GMAC_FLOWCTRL_MASK = (1 << RK3288_GMAC_FLOWCTRL_SHIFT),
RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
- HOST_REMAP_SHIFT = 0x5,
- HOST_REMAP_MASK = 1
+ RK3288_HOST_REMAP_SHIFT = 0x5,
+ RK3288_HOST_REMAP_MASK = (1 << RK3288_HOST_REMAP_SHIFT),
};
/* GRF_SOC_CON2 */
--
2.39.5
