If the MII interface is used, the PHY is the clock master, thus don't
set the clock rate. On Zynq-7000, this will prevent the following
error:
  zynq_gem ethernet@e000b000: failed to set tx clock rate 25000000

Signed-off-by: Martin Kaistra <martin.kais...@linutronix.de>
---
 drivers/net/zynq_gem.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 461805ae53f..703e22479d2 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -567,12 +567,14 @@ static int zynq_gem_init(struct udevice *dev)
        }
 #endif
 
-       ret = clk_get_rate(&priv->tx_clk);
-       if (ret != clk_rate) {
-               ret = clk_set_rate(&priv->tx_clk, clk_rate);
-               if (IS_ERR_VALUE(ret)) {
-                       dev_err(dev, "failed to set tx clock rate %ld\n", 
clk_rate);
-                       return ret;
+       if (priv->interface != PHY_INTERFACE_MODE_MII) {
+               ret = clk_get_rate(&priv->tx_clk);
+               if (ret != clk_rate) {
+                       ret = clk_set_rate(&priv->tx_clk, clk_rate);
+                       if (IS_ERR_VALUE(ret)) {
+                               dev_err(dev, "failed to set tx clock rate 
%ld\n", clk_rate);
+                               return ret;
+                       }
                }
        }
 
-- 
2.39.5

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