On 24/03/2025 23:05, Marek Vasut wrote:
> On 3/24/25 11:12 AM, Paul Barker wrote:
>> On 24/03/2025 01:11, Marek Vasut wrote:
>>> On 3/19/25 1:03 PM, Paul Barker wrote:
>>>
>>> [...]
>>>
>>>> +++ b/drivers/net/Kconfig
>>>> @@ -864,7 +864,7 @@ config RENESAS_RAVB
>>>> select PHY_ETHERNET_ID
>>>> help
>>>> This driver implements support for the Ethernet AVB block in
>>>> - Renesas M3 and H3 SoCs.
>>>> + several Renesas R-Car and RZ SoCs.
>>>
>>> RZ/G instead of RZ , right ?
>>
>> This will also be used for RZ/V2L.
>
> Ahh, thank you for clarifying.
>
> [...]
>
>>>> +static void ravb_mac_init_rzg2l(struct udevice *dev)
>>>> +{
>>>> + struct ravb_priv *eth = dev_get_priv(dev);
>>>> +
>>>> + setbits_32(eth->iobase + RAVB_REG_ECMR,
>>>> + ECMR_PRM | ECMR_RXF | ECMR_TXF | ECMR_RCPT |
>>>> + ECMR_TE | ECMR_RE | ECMR_RZPF |
>>>> + (eth->phydev->duplex ? ECMR_DM : 0));
>>>
>>> Can you configure the ECMR extras in ravb_config() just before
>>> writel(mask, eth->iobase + RAVB_REG_ECMR); based on some private data
>>> flag, like '.is_rzg2l' , instead ?
>>
>> ravb_config() has been split into ravb_config_rcar() &
>> ravb_config_rzg2l() by this patch series. So there is no longer a common
>> write to RAVB_REG_ECMR.
>>
>>>
>>>> +}
>>>> +
>>>> /* AVB-DMAC init function */
>>>> static int ravb_dmac_init(struct udevice *dev)
>>>> {
>>>> @@ -459,6 +481,14 @@ static void ravb_dmac_init_rcar(struct udevice *dev)
>>>> writel(mode, eth->iobase + RAVB_REG_APSR);
>>>> }
>>>>
>>>> +static void ravb_dmac_init_rzg2l(struct udevice *dev)
>>>> +{
>>>> + struct ravb_priv *eth = dev_get_priv(dev);
>>>> +
>>>> + /* Set Max Frame Length (RTC) */
>>>> + writel(0x7ffc0000 | RFLR_RFL_MIN, eth->iobase + RAVB_REG_RTC);
>>>
>>> I assume this register is actually RZ/G2L specific ?
>>
>> This register also exists on RZ/G2{H,M,N,E}, but in the Linux kernel
>> ravb driver it is only modified for RZ/G2L.
>
> Is this deliberate or is that a bug ?Hi Marek, The RTC register exists in RZ/G2H family, R-Car Gen3 and R-Car Gen4. It may also exist in R-Car Gen5, I don't have visibility into the Ethernet registers for the Gen5 yet. Given that Ethernet is working on those platforms where the RTC register is present but is not modified by the driver, I've aimed to avoid any potential change in behaviour by limiting this register modification to the RZ/G2L. Thanks, -- Paul Barker
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