On Tue, Apr 15, 2025 at 09:43:12AM -0500, Adam Ford wrote:
> On Tue, Apr 15, 2025 at 9:28 AM Francesco Dolcini <france...@dolcini.it>
> wrote:
> >
> > Hello Marex, Fabio, all
> >
> > On Sun, Mar 23, 2025 at 04:58:45PM +0100, Marek Vasut wrote:
> > > Convert clock-osc-24m back to osc_24m and clock-osc-32k back to osc_32k.
> > > These are the clock which match clock tables in Linux. This is now
> > > possible because the clock drivers now resolve clock names based on
> > > clock-names DT property in the CCM DT node.
> > >
> > > Signed-off-by: Marek Vasut <ma...@denx.de>
> >
> > Current USB fastboot functionality from U-Boot proper in master is broken
> > on Verdin iMX8M Plus since commit b4734c9c333b ("clk: imx: Convert
> > clock-osc-* back to osc_*"). Other i.MX SoCs might be affected, I have
> > not looked into every detail.
> >
> > Could not fetch index
> > Failed to get PHY0 for usb@38100000
> > Could not fetch index
> > Failed to get PHY0 for usb@38100000
> > No USB device found
> > USB init failed: -19
> >
> > Reverting this commit on top of master is not trivial (there are
> > conflicts, and I have not looked into the details).
> >
> > Full log for reference
> >
> > U-Boot SPL 2025.04-rc4-00537-gb4734c9c333b (Apr 15 2025 - 16:14:09 +0200)
> > Training FAILED
> > DDR configured as single rank
> > WDT: Started watchdog@30280000 with servicing every 1000ms (60s timeout)
> > SEC0: RNG instantiated
> > Normal Boot
> > Trying to boot from BOOTROM
> > Boot Stage: USB boot
> > Find img info 0x4802ec00, size 1116
> > Need continue download 1024
> > NOTICE: Do not release JR0 to NS as it can be used by HAB
> > NOTICE: BL31: v2.12.0(release):v2.12.0-946-g4d913df8f85e
> > NOTICE: BL31: Built : 13:19:07, Apr 15 2025
> >
> >
> > U-Boot 2025.04-rc4-00537-gb4734c9c333b (Apr 15 2025 - 16:14:09 +0200)
> >
> > CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
> > CPU: Industrial temperature grade (-40C to 105C) at 56C
> > Reset cause: POR
> > DRAM: 4 GiB
> > Core: 309 devices, 31 uclasses, devicetree: separate
> > WDT: Started watchdog@30280000 with servicing every 1000ms (60s timeout)
> > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > Loading Environment from nowhere... OK
> > In: serial@30880000
> > Out: serial@30880000
> > Err: serial@30880000
> > Model: Toradex 0058 Verdin iMX8M Plus Quad 4GB WB IT V1.0B
> > Serial#: 06849144
> > Carrier: Toradex Dahlia V1.1A, Serial# 10763256
> > SEC0: RNG instantiated
> > Setting variant to wifi
> > Net: pca953x gpio-expander@21: Error reading output register
> > eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
> > Hit any key to stop autoboot: 0
> > Could not fetch index
> > Failed to get PHY0 for usb@38100000
> > Could not fetch index
> > Failed to get PHY0 for usb@38100000
>
> When running my 8M Plus in Host mode, I got similar "Failed to get
> PHY0 for usb" failures, but I hadn't yet bisected it. The PHY itself
> doesn't appear to have a clock reference itself, but it does reference
> a power-domain which uses multiple clocks. I wonder if one of the
> clocks in the hsio power domain isn't registering properly. I won't
> be near my 8MP until much later tonight, but can you run 'dm tree' to
> see what clocks are enumerated and which might be missing?
Here the logs,
https://gist.github.com/dolcini/035ede9e94026c8f7f34e64ee07e124b
commit bcb141d11428 ("clk: imx: Pass struct udevice into
imx_clk_composite*()") is the last good, commit b4734c9c333b ("clk: imx:
Convert clock-osc-* back to osc_*") is the first bad.
Francesco
