Hi Ilias,
On Wed, 19 Mar 2025 at 08:22, Ilias Apalodimas
<ilias.apalodi...@linaro.org> wrote:
>
> We currently set both and print both PXN and UXN bits when removing
> execution for pages. This happens even in the existing per platform
> definitions of 'struct mm_region'.
>
> That's not entirely correct though. For stage-1 translations, if a
> platform runs on a translation regime with a single privilege level or the
> the translation regime supports two privilege levels and we are not
> in EL1&0 with HCR_EL2.{NV, NV1} = {1, 1} only BIT54 (XN) is needed
> and BIT53(PXN) is reserved 0.
>
> Currently we support Non-Secure EL2, Non-secure EL2&0 and Non-secure
> EL1&0.
>
> We already have get_effective_el() which returns 1 if we are
> - Running in EL1 so we assume an EL1 translation regime but without
> checking HCR_EL2.{NV, NV1} != {1,1}
> - Running in EL2 with HCR_EL2.E2H = 1
>
> The only problem with the above is that if we are in EL1&0 and
> HCR_EL2.{NV1, NV} == {1, 1}, then
> - Bit[54] holds the PXN instead of the UXN
> - The Effective value of UXN is 0
> - Bit[53] is RES0
>
> So let's re-use that function and set PXN only when we are in
> and EL[2|1]&0 translation regime.
>
> Signed-off-by: Ilias Apalodimas <ilias.apalodi...@linaro.org>
> ---
> arch/arm/cpu/armv8/cache_v8.c | 28 ++++++++++++++++++++++++----
> 1 file changed, 24 insertions(+), 4 deletions(-)
>
Perhaps add a test?
Regards,
Simon
