Since the opcode SPINOR_OP_CHIP_ERASE (0xc7) is not supported
for the mt35xu01g/2g flashes, the NO_CHIP_ERASE flag has been added
to enable sector erase functionality instead.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbar...@amd.com>
---
drivers/mtd/spi/spi-nor-ids.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 91ae49c9484..44d08752011 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -358,10 +358,13 @@ const struct flash_info spi_nor_ids[] = {
#ifdef CONFIG_SPI_FLASH_MT35XU
{ INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
- { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024, USE_FSR |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
NO_CHIP_ERASE) },
#endif /* CONFIG_SPI_FLASH_MT35XU */
- { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
- { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
NO_CHIP_ERASE) },
+ { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
NO_CHIP_ERASE) },
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
/* Spansion/Cypress -- single (large) sector size only, at least
--
2.25.1
