To be able to return to the BootROM when booting via the FEL USB
protocol, we need to save the CPU state very early, which we need to do
in the embedded AArch32 code. At the moment the pointer to the buffer for
that state is located *after* the code, which makes the PC relative
code fragile: adding or removing instructions will change the distance
to that pointer variable.
The "new" Allwinner A523 SoC requires more state to be saved (GICv3
system registers), but we must do that *only* on that SoC. Conditional
compilation sounds like the easiest solution, but would mean that the
distance to that pointer would change.
Solve this rather easily by moving the pointer to the *front* of the
code: we load that pointer in the first instructions, so the distance
would always stay the same. Later in the code we won't need PC relative
addressing anymore, so this code can grow or shrink easily, for instance
due to conditional compilation.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm/include/asm/arch-sunxi/boot0.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h
b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6b2bb5a4586..24c81391d58 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -16,10 +16,11 @@
*/
tst x0, x0 // this is "b #0x84" in ARM
b reset
- .space 0x7c
+ .space 0x78
+ .word fel_stash - .
- .word 0xe28f0070 // add r0, pc, #112 // @(fel_stash - .)
- .word 0xe59f106c // ldr r1, [pc, #108] // fel_stash - .
+ .word 0xe24f000c // sub r0, pc, #12 // @(fel_stash - .)
+ .word 0xe51f1010 // ldr r1, [pc, #-16] // fel_stash - .
.word 0xe0800001 // add r0, r0, r1
.word 0xe580d000 // str sp, [r0]
.word 0xe580e004 // str lr, [r0, #4]
@@ -54,7 +55,6 @@
#else
.word CONFIG_TEXT_BASE
#endif
- .word fel_stash - .
#else
/* normal execution */
b reset
--
2.46.3
