On 3/11/25 9:57 PM, Paul Barker wrote:
Add a new driver to control the USB 2.0 PHY reset controller on the Renesas RZ/G2L and related SoCs.Signed-off-by: Paul Barker <paul.barker...@bp.renesas.com> --- drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-rzg2l-usbphy-ctrl.c | 113 ++++++++++++++++++++++++ include/renesas/rzg2l-usbphy.h | 17 ++++ 4 files changed, 140 insertions(+) create mode 100644 drivers/reset/reset-rzg2l-usbphy-ctrl.c create mode 100644 include/renesas/rzg2l-usbphy.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index fe5c1214f57a..80e83a40bdff 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -235,4 +235,13 @@ config RESET_AT91 This enables the Reset Controller driver support for Microchip/Atmel SoCs. Mainly used to expose assert/deassert methods to other drivers that require it. + +config RESET_RZG2L_USBPHY_CTRL + bool "Enable support for Renesas RZ/G2L USB 2.0 PHY control" + depends on DM_RESET + help + Enable support for controlling USB 2.0 PHY resets on the Renesas + RZ/G2L SoC. This is required for USB 2.0 functionality to work on this + SoC. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index d99a78c9828b..9d438a755b30 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -33,3 +33,4 @@ obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o obj-$(CONFIG_RESET_DRA7) += reset-dra7.o obj-$(CONFIG_RESET_AT91) += reset-at91.o obj-$(CONFIG_$(PHASE_)RESET_JH7110) += reset-jh7110.o +obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c new file mode 100644 index 000000000000..afd647e00b19 --- /dev/null +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corporation
Maybe this should be 2025 now ? Reviewed-by: Marek Vasut <marek.vasut+rene...@mailbox.org> Thanks !
