[PATCH v3 2/8] clk: at91: sam9x60-pll: add support for core clock frequency inputs

[Manikandan Muralidharan]

From: Varshini Rajendran <varshini.rajend...@microchip.com>

Add support for different core clock frequency input ranges
for different PLL IDs in the PLL driver and align sam9x60, sama7g5 SOC
platforms.

Signed-off-by: Varshini Rajendran <varshini.rajend...@microchip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 17 ++++++++---------
 drivers/clk/at91/pmc.h             |  1 +
 drivers/clk/at91/sam9x60.c         |  7 +++++++
 drivers/clk/at91/sama7g5.c         |  6 ++++++
 4 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c 
b/drivers/clk/at91/clk-sam9x60-pll.c
index a30035eb8ce..676ad8294a6 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -31,9 +31,6 @@
 #define UPLL_DIV               2
 #define PLL_MUL_MAX            (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
 
-#define FCORE_MIN              (600000000)
-#define FCORE_MAX              (1200000000)
-
 #define PLL_MAX_ID             7
 
 struct sam9x60_pll {
@@ -55,14 +52,15 @@ static inline bool sam9x60_pll_ready(void __iomem *base, 
int id)
        return !!(status & BIT(id));
 }
 
-static long sam9x60_frac_pll_compute_mul_frac(u32 *mul, u32 *frac, ulong rate,
+static long sam9x60_frac_pll_compute_mul_frac(const struct clk_range *core_clk,
+                                             u32 *mul, u32 *frac, ulong rate,
                                              ulong parent_rate)
 {
        unsigned long tmprate, remainder;
        unsigned long nmul = 0;
        unsigned long nfrac = 0;
 
-       if (rate < FCORE_MIN || rate > FCORE_MAX)
+       if (rate < core_clk->min || rate > core_clk->max)
                return -ERANGE;
 
        /*
@@ -82,7 +80,7 @@ static long sam9x60_frac_pll_compute_mul_frac(u32 *mul, u32 
*frac, ulong rate,
        }
 
        /* Check if resulted rate is valid.  */
-       if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
+       if (tmprate < core_clk[0].min || tmprate > core_clk[0].max)
                return -ERANGE;
 
        *mul = nmul - 1;
@@ -103,8 +101,8 @@ static ulong sam9x60_frac_pll_set_rate(struct clk *clk, 
ulong rate)
        if (!parent_rate)
                return 0;
 
-       ret = sam9x60_frac_pll_compute_mul_frac(&nmul, &nfrac, rate,
-                                               parent_rate);
+       ret = 
sam9x60_frac_pll_compute_mul_frac(pll->characteristics->core_output,
+                                               &nmul, &nfrac, rate, 
parent_rate);
        if (ret < 0)
                return 0;
 
@@ -163,7 +161,8 @@ static int sam9x60_frac_pll_enable(struct clk *clk)
        ulong crate;
 
        crate = sam9x60_frac_pll_get_rate(clk);
-       if (crate < FCORE_MIN || crate > FCORE_MAX)
+       if (crate < pll->characteristics->core_output[0].min ||
+           crate > pll->characteristics->core_output[0].max)
                return -ERANGE;
 
        pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index ff464522aa0..49134531564 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -38,6 +38,7 @@ struct clk_pll_characteristics {
        struct clk_range input;
        int num_output;
        const struct clk_range *output;
+       const struct clk_range *core_output;
        u16 *icpll;
        u8 *out;
        u8 upll : 1;
diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index b7d64bdbb3d..e04266a2be2 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -112,17 +112,24 @@ static const struct clk_range upll_outputs[] = {
        { .min = 300000000, .max = 500000000 },
 };
 
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+       { .min = 600000000, .max = 1200000000 },
+};
+
 /* PLL characteristics. */
 static const struct clk_pll_characteristics apll_characteristics = {
        .input = { .min = 12000000, .max = 48000000 },
        .num_output = ARRAY_SIZE(plla_outputs),
        .output = plla_outputs,
+       .core_output = core_outputs,
 };
 
 static const struct clk_pll_characteristics upll_characteristics = {
        .input = { .min = 12000000, .max = 48000000 },
        .num_output = ARRAY_SIZE(upll_outputs),
        .output = upll_outputs,
+       .core_output = core_outputs,
        .upll = true,
 };
 
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 63b2c647467..c0e27828b1a 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -158,11 +158,17 @@ static const struct clk_range pll_outputs[] = {
        { .min = 2343750, .max = 1200000000 },
 };
 
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+       { .min = 600000000, .max = 1200000000 },
+};
+
 /* PLL characteristics. */
 static const struct clk_pll_characteristics pll_characteristics = {
        .input = { .min = 12000000, .max = 50000000 },
        .num_output = ARRAY_SIZE(pll_outputs),
        .output = pll_outputs,
+       .core_output = core_outputs,
 };
 
 /* Layout for fractional PLLs. */
-- 
2.25.1