Add initial set of clocks and resets for enabling U-Boot on ipq5424
based RDP platforms.
Signed-off-by: Varadarajan Narayanan <quic_var...@quicinc.com>
---
drivers/clk/qcom/Kconfig | 8 +++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-ipq5424.c | 96 ++++++++++++++++++++++++++++++++
drivers/clk/qcom/clock-qcom.h | 1 +
4 files changed, 106 insertions(+)
create mode 100644 drivers/clk/qcom/clock-ipq5424.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 3ea01f3c96..6c44a6549a 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019
on the Snapdragon IPQ4019 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_IPQ5424
+ bool "Qualcomm IPQ5424 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Qualcomm IPQ5424 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
config CLK_QCOM_IPQ9574
bool "Qualcomm IPQ9574 GCC"
select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index e13fc8c107..3ce31dd167 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
+obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o
obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
diff --git a/drivers/clk/qcom/clock-ipq5424.c b/drivers/clk/qcom/clock-ipq5424.c
new file mode 100644
index 0000000000..40823a30ea
--- /dev/null
+++ b/drivers/clk/qcom/clock-ipq5424.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock drivers for Qualcomm ipq5424
+ *
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
+#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
+
+#include "clock-qcom.h"
+
+#define GCC_IM_SLEEP_CBCR 0x1834020u
+
+static ulong ipq5424_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case GCC_QUPV3_UART1_CLK:
+ clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].reg,
+ 0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
+ return rate;
+ case GCC_SDCC1_APPS_CLK:
+ clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].reg,
+ 5, 0, 0, CFG_CLK_SRC_GPLL2_MAIN, 16);
+ return rate;
+ }
+ return 0;
+}
+
+static const struct gate_clk ipq5424_clks[] = {
+ GATE_CLK(GCC_QUPV3_UART1_CLK, 0x302c, BIT(0)),
+ GATE_CLK(GCC_SDCC1_AHB_CLK, 0x3303c, BIT(0)),
+ GATE_CLK(GCC_SDCC1_APPS_CLK, 0x33004, BIT(1)),
+ GATE_CLK(GCC_IM_SLEEP_CLK, 0x34020, BIT(0)),
+};
+
+static int ipq5424_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id >= ARRAY_SIZE(ipq5424_clks) || !ipq5424_clks[clk->id].reg)
+ return -EINVAL;
+
+ qcom_gate_clk_en(priv, clk->id);
+
+ return 0;
+}
+
+static const struct qcom_reset_map ipq5424_gcc_resets[] = {
+ [GCC_SDCC_BCR] = { 0x33000 },
+};
+
+static struct msm_clk_data ipq5424_gcc_data = {
+ .resets = ipq5424_gcc_resets,
+ .num_resets = ARRAY_SIZE(ipq5424_gcc_resets),
+ .clks = ipq5424_clks,
+ .num_clks = ARRAY_SIZE(ipq5424_clks),
+
+ .enable = ipq5424_enable,
+ .set_rate = ipq5424_set_rate,
+};
+
+static const struct udevice_id gcc_ipq5424_of_match[] = {
+ {
+ .compatible = "qcom,ipq5424-gcc",
+ .data = (ulong)&ipq5424_gcc_data,
+ },
+ { }
+};
+
+static int ipq5424_clk_probe(struct udevice *dev)
+{
+ /* Enable the sleep clock needed for the MMC block reset */
+ writel(BIT(0), GCC_IM_SLEEP_CBCR);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gcc_ipq5424) = {
+ .name = "gcc_ipq5424",
+ .id = UCLASS_NOP,
+ .of_match = gcc_ipq5424_of_match,
+ .probe = ipq5424_clk_probe,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index e038dc421e..2a01fb84a4 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -12,6 +12,7 @@
#define CFG_CLK_SRC_GPLL0 (1 << 8)
#define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
#define CFG_CLK_SRC_GPLL2 (2 << 8)
+#define CFG_CLK_SRC_GPLL2_MAIN (2 << 8)
#define CFG_CLK_SRC_GPLL9 (2 << 8)
#define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
#define CFG_CLK_SRC_GPLL6 (4 << 8)
--
2.34.1
