пн, 3 бер. 2025 р. о 19:06 Tom Rini <tr...@konsulko.com> пише: > > On Mon, Mar 03, 2025 at 09:31:37AM -0300, Fabio Estevam wrote: > > Hi Miquel, > > > > On Wed, Jan 29, 2025 at 7:22 AM Miquel Raynal <miquel.ray...@bootlin.com> > > wrote: > > > > > > In order to display a boot picture or an error message, the i.MX8MP > > > display pipeline must be enabled. The SoC has support for various > > > interfaces (LVDS, HDMI, DSI). The one supported in this series is the > > > standard 4-lane LVDS output. The minimal setup is thus composed of: > > > * An LCD InterFace (LCDIF) with an AXI/APB interface, generating a pixel > > > stream > > > * One LVDS Display Bridge (LDB), also named pixel mapper, which receives > > > the pixel stream and route it to one or two (possibly combined) LVDS > > > displays. > > > * All necessary clocks and power controls coming from the MEDIAMIX > > > control block. > > > > I am seeing the following CI error in sandbox_spl test.py with this > > series applied: > > > > https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/1045491 > > > > Please take a look. > > It's a tangential failure. Svyatoslav reported this with a series he's > working on and Simon wonders if bloblist support got broken but hasn't > had time to look at it. >
If seems that we are working on the same OF graph stuff > -- > Tom
