Add a driver for Qualcomm's sc7180 pinctrl device (TLMM). This is
largely a copy of a similar driver in U-Boot along with reference to the
Linux driver to fix up the data properly.
Signed-off-by: Stephen Boyd <swb...@chromium.org>
---
drivers/pinctrl/qcom/Kconfig | 7 ++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sc7180.c | 106 ++++++++++++++++++++++++++
3 files changed, 114 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7180.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d3eb69985510..4772daba1ef3 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -41,6 +41,13 @@ config PINCTRL_QCOM_QCS404
Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_SC7180
+ bool "Qualcomm SC7180 Pinctrl (TLMM)"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon SC7180 SoC,
+ as well as the associated GPIO driver.
+
config PINCTRL_QCOM_SDM845
bool "Qualcomm SDM845 GCC"
select PINCTRL_QCOM
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 06d3c95f93a6..ac5dfd1feb91 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
+obj-$(CONFIG_PINCTRL_QCOM_SC7180) += pinctrl-sc7180.o
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c
b/drivers/pinctrl/qcom/pinctrl-sc7180.c
new file mode 100644
index 000000000000..1edc74e5da95
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SC7180 pinctrl
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define WEST 0x00000000
+#define NORTH 0x00400000
+#define SOUTH 0x00800000
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"qup12", 1},
+ {"gpio", 0},
+};
+
+static const unsigned int sc7180_pin_offsets[] = {
+ [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, [4] = NORTH,
+ [5] = NORTH, [6] = NORTH, [7] = NORTH, [8] = NORTH, [9] = NORTH,
+ [10] = NORTH, [11] = NORTH, [12] = SOUTH, [13] = SOUTH, [14] = SOUTH,
+ [15] = SOUTH, [16] = SOUTH, [17] = SOUTH, [18] = SOUTH, [19] = SOUTH,
+ [20] = SOUTH, [21] = NORTH, [22] = NORTH, [23] = SOUTH, [24] = SOUTH,
+ [25] = SOUTH, [26] = SOUTH, [27] = SOUTH, [28] = SOUTH, [29] = NORTH,
+ [30] = SOUTH, [31] = NORTH, [32] = NORTH, [33] = NORTH, [34] = SOUTH,
+ [35] = SOUTH, [36] = SOUTH, [37] = SOUTH, [38] = SOUTH, [39] = SOUTH,
+ [40] = SOUTH, [41] = SOUTH, [42] = NORTH, [43] = NORTH, [44] = NORTH,
+ [45] = NORTH, [46] = NORTH, [47] = NORTH, [48] = NORTH, [49] = WEST,
+ [50] = WEST, [51] = WEST, [52] = WEST, [53] = WEST, [54] = WEST,
+ [55] = WEST, [56] = WEST, [57] = WEST, [58] = WEST, [59] = NORTH,
+ [60] = NORTH, [61] = NORTH, [62] = NORTH, [63] = NORTH, [64] = NORTH,
+ [65] = NORTH, [66] = NORTH, [67] = NORTH, [68] = NORTH, [69] = WEST,
+ [70] = NORTH, [71] = NORTH, [72] = NORTH, [73] = WEST, [74] = WEST,
+ [75] = WEST, [76] = WEST, [77] = WEST, [78] = WEST, [79] = WEST,
+ [80] = WEST, [81] = WEST, [82] = WEST, [83] = WEST, [84] = WEST,
+ [85] = WEST, [86] = NORTH, [87] = NORTH, [88] = NORTH, [89] = NORTH,
+ [90] = NORTH, [91] = NORTH, [92] = NORTH, [93] = NORTH, [94] = SOUTH,
+ [95] = WEST, [96] = WEST, [97] = WEST, [98] = WEST, [99] = WEST,
+ [100] = WEST, [101] = NORTH, [102] = NORTH, [103] = NORTH, [104] = WEST,
+ [105] = NORTH, [106] = NORTH, [107] = WEST, [108] = SOUTH, [109] =
SOUTH,
+ [110] = NORTH, [111] = NORTH, [112] = NORTH, [113] = NORTH, [114] =
NORTH,
+ [115] = WEST, [116] = WEST, [117] = WEST, [118] = WEST,
+};
+
+static const char *sc7180_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sc7180_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ static const char * const special_pins_names[] = {
+ "ufs_reset",
+ "sdc1_rclk",
+ "sdc1_clk",
+ "sdc1_cmd",
+ "sdc1_data",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
+ };
+
+ if (selector >= 119 && selector <= 126)
+ snprintf(pin_name, MAX_PIN_NAME_LEN,
special_pins_names[selector - 119]);
+ else
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+ return pin_name;
+}
+
+static unsigned int sc7180_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+static const struct msm_pinctrl_data sc7180_data = {
+ .pin_data = {
+ .pin_offsets = sc7180_pin_offsets,
+ .pin_count = 127,
+ .special_pins_start = 119,
+ },
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = sc7180_get_function_name,
+ .get_function_mux = sc7180_get_function_mux,
+ .get_pin_name = sc7180_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,sc7180-pinctrl", .data = (ulong)&sc7180_data },
+ { /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sc7180) = {
+ .name = "pinctrl_sc7180",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
--
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