On 2/11/25 13:49, Bernhard Messerklinger wrote:
This commit adds support for the brcp1, brsmarc2, brcp150 and brcp170
boards. This boards are based on the Xilinx Zynq SoC.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com>
---
Changes in v2:
- Remove all unnecessary device-tree entries
- Reviewed led names (no pattern restriction found)
- Fix maintainers file
- Cleanup of code
- Move preboot variable to env file
arch/arm/dts/Makefile | 8 +-
arch/arm/dts/zynq-brcp1-u-boot.dtsi | 110 +++++++
arch/arm/dts/zynq-brcp1.dtsi | 133 +++++++++
arch/arm/dts/zynq-brcp150-u-boot.dtsi | 129 ++++++++
arch/arm/dts/zynq-brcp150.dts | 174 +++++++++++
arch/arm/dts/zynq-brcp170-u-boot.dtsi | 113 +++++++
arch/arm/dts/zynq-brcp170.dts | 140 +++++++++
arch/arm/dts/zynq-brcp1_1r.dts | 29 ++
arch/arm/dts/zynq-brcp1_1r_switch.dts | 30 ++
arch/arm/dts/zynq-brcp1_2r.dts | 22 ++
arch/arm/dts/zynq-brsmarc2-u-boot.dtsi | 110 +++++++
arch/arm/dts/zynq-brsmarc2.dts | 158 ++++++++++
arch/arm/mach-zynq/Kconfig | 1 +
board/BuR/zynq/Kconfig | 14 +
board/BuR/zynq/MAINTAINERS | 11 +
board/BuR/zynq/Makefile | 15 +
board/BuR/zynq/brcp150/board.c | 4 +
board/BuR/zynq/brcp150/ps7_init_gpl.c | 278 ++++++++++++++++++
board/BuR/zynq/brcp170/board.c | 4 +
board/BuR/zynq/brcp170/ps7_init_gpl.c | 274 +++++++++++++++++
board/BuR/zynq/brcp1_1r/board.c | 4 +
board/BuR/zynq/brcp1_1r/ps7_init_gpl.c | 274 +++++++++++++++++
board/BuR/zynq/brcp1_1r_switch/board.c | 4 +
board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c | 270 +++++++++++++++++
board/BuR/zynq/brcp1_2r/board.c | 4 +
board/BuR/zynq/brcp1_2r/ps7_init_gpl.c | 277 +++++++++++++++++
board/BuR/zynq/brsmarc2/board.c | 30 ++
board/BuR/zynq/brsmarc2/ps7_init_gpl.c | 276 +++++++++++++++++
board/BuR/zynq/common/board.c | 231 +++++++++++++++
board/BuR/zynq/env/brcp1.env | 109 +++++++
board/BuR/zynq/env/brcp150.env | 119 ++++++++
configs/brcp150_defconfig | 123 ++++++++
configs/brcp170_defconfig | 122 ++++++++
configs/brcp1_1r_defconfig | 122 ++++++++
configs/brcp1_1r_switch_defconfig | 123 ++++++++
configs/brcp1_2r_defconfig | 122 ++++++++
configs/brsmarc2_defconfig | 122 ++++++++
include/configs/brzynq.h | 21 ++
38 files changed, 4109 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynq-brcp1-u-boot.dtsi
create mode 100644 arch/arm/dts/zynq-brcp1.dtsi
create mode 100644 arch/arm/dts/zynq-brcp150-u-boot.dtsi
create mode 100644 arch/arm/dts/zynq-brcp150.dts
create mode 100644 arch/arm/dts/zynq-brcp170-u-boot.dtsi
create mode 100644 arch/arm/dts/zynq-brcp170.dts
create mode 100644 arch/arm/dts/zynq-brcp1_1r.dts
create mode 100644 arch/arm/dts/zynq-brcp1_1r_switch.dts
create mode 100644 arch/arm/dts/zynq-brcp1_2r.dts
create mode 100644 arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
create mode 100644 arch/arm/dts/zynq-brsmarc2.dts
create mode 100644 board/BuR/zynq/Kconfig
create mode 100644 board/BuR/zynq/MAINTAINERS
create mode 100644 board/BuR/zynq/Makefile
create mode 100644 board/BuR/zynq/brcp150/board.c
create mode 100644 board/BuR/zynq/brcp150/ps7_init_gpl.c
create mode 100644 board/BuR/zynq/brcp170/board.c
create mode 100644 board/BuR/zynq/brcp170/ps7_init_gpl.c
create mode 100644 board/BuR/zynq/brcp1_1r/board.c
create mode 100644 board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
create mode 100644 board/BuR/zynq/brcp1_1r_switch/board.c
create mode 100644 board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
create mode 100644 board/BuR/zynq/brcp1_2r/board.c
create mode 100644 board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
create mode 100644 board/BuR/zynq/brsmarc2/board.c
create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c
create mode 100644 board/BuR/zynq/common/board.c
create mode 100644 board/BuR/zynq/env/brcp1.env
create mode 100644 board/BuR/zynq/env/brcp150.env
create mode 100644 configs/brcp150_defconfig
create mode 100644 configs/brcp170_defconfig
create mode 100644 configs/brcp1_1r_defconfig
create mode 100644 configs/brcp1_1r_switch_defconfig
create mode 100644 configs/brcp1_2r_defconfig
create mode 100644 configs/brsmarc2_defconfig
create mode 100644 include/configs/brzynq.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0bf3697bdbe..35eb169a853 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -241,7 +241,13 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zturn.dtb \
zynq-zturn-v5.dtb \
zynq-zybo.dtb \
- zynq-zybo-z7.dtb
+ zynq-zybo-z7.dtb \
I prefer if you can build it only for your target
TARGET_ZYNQ_BR
+ zynq-brcp1_2r.dtb \
+ zynq-brcp1_1r.dtb \
+ zynq-brcp1_1r_switch.dtb \
+ zynq-brsmarc2.dtb \
+ zynq-brcp150.dtb \
+ zynq-brcp170.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
zynqmp-a2197-revA.dtb \
diff --git a/arch/arm/dts/zynq-brcp1-u-boot.dtsi
b/arch/arm/dts/zynq-brcp1-u-boot.dtsi
new file mode 100644
index 00000000000..3e1d157abc1
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1-u-boot.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include <config.h>
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+ spi_flash: spiflash@0 {
+ bootph-all;
I would use
&spi_flash {
bootph-all;
};
this will avoid duplication of node name.
Also it can avoid creating new node name if origin is chagned.
+ };
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
+
+/ {
+ binman {
+ bootph-all;
+ filename = "flash.bin";
+ pad-byte = <0xff>;
+ align-size = <16>;
+ align = <16>;
I compared these 3
arch/arm/dts/zynq-brcp150-u-boot.dtsi
arch/arm/dts/zynq-brcp1-u-boot.dtsi
arch/arm/dts/zynq-brcp170-u-boot.dtsi
and binman description is pretty much the same. Difference is only in blob-ext
nodes which are optional anyway.
Isn't easier for you instead of maintaining 3 copies of the same description
just to use only one?
If yes you can look at how I did wire Kria like this
CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-som.dtb"
you can keep binman node separated out of your regular DT.
And if you don't want to have it separated you can still put it to own file and
source it from here.
+
+ blob@0 {
+ filename = "spl/boot.bin";
+ offset = <0x0>;
+ };
+
+ fit {
+ description = "U-Boot BR Zynq boards";
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+
+ images {
+ uboot {
+ description = "U-Boot BR Zynq";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ u-boot-nodtb {
+ };
+ };
+
+ fdt-0 {
+ description = "DTB BR Zynq";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ u-boot-dtb {
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "BR Zynq";
+ firmware = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+
+ blob-ext@0 {
+ filename = "blobs/cfg.img";
+ offset = <0xC0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@1 {
+ bootph-all;
+ filename = "blobs/bitstream.bit";
+ offset = <0x100000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@2 {
+ filename = "blobs/bootar.itb";
+ offset = <0x900000>;
+ size = <0x600000>;
+ optional;
+ };
+
+ blob-ext@3 {
+ filename = "blobs/dtb.bin";
+ offset = <0xF00000>;
+ size = <0x100000>;
+ optional;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi
new file mode 100644
index 00000000000..f1cf75f1277
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP1 CPU";
+ compatible = "br,cp1",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+#include "zynq-brcp1-u-boot.dtsi"
Why? It should be added automatically when you run build.
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+
+ pmic0: da9062@58 {
+ compatible = "dlg,da9062";
+ reg = <0x58>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+ max-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi
b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
new file mode 100644
index 00000000000..f2771dd9bda
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include <config.h>
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+ spi_flash: spiflash@0 {
+ bootph-all;
+ };
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
+
+&rs232_en {
+ bootph-all;
+};
+
+/ {
+ binman {
+ bootph-all;
+ filename = "flash.bin";
+ pad-byte = <0xff>;
+ align-size = <16>;
+ align = <16>;
+
+ blob@0 {
+ filename = "spl/boot.bin";
+ offset = <0x0>;
+ };
+
+ fit {
+ description = "U-Boot BR Zynq boards";
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+
+ images {
+ uboot {
+ description = "U-Boot BR Zynq";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ u-boot-nodtb {
+ };
+ };
+
+ fdt-0 {
+ description = "DTB BR Zynq";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ u-boot-dtb {
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "BR Zynq";
+ firmware = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+
+ blob-ext@0 {
+ filename = "blobs/cfg.img";
+ offset = <0xC0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@5 {
+ filename = "blobs/cfg_opt.img";
+ offset = <0xD0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@1 {
+ bootph-all;
+ filename = "blobs/bitstream.bit";
+ offset = <0x100000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@4 {
+ bootph-all;
+ filename = "blobs/bitstream_update.bit";
+ offset = <0x400000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@2 {
+ filename = "blobs/bootar.itb";
+ offset = <0x900000>;
+ size = <0x600000>;
+ optional;
+ };
+
+ blob-ext@3 {
+ filename = "blobs/dtb.bin";
+ offset = <0xF00000>;
+ size = <0x100000>;
+ optional;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp150.dts b/arch/arm/dts/zynq-brcp150.dts
new file mode 100644
index 00000000000..bf2facb10c7
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150.dts
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP150 CPU";
+ compatible = "br,cp150",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* Put this pin active high to enable RS232 debug serial */
+ rs232_en: rs232_enable {
+ compatible = "br,rs232-en";
+ pin = <&gpio0 52 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_red {
+ label = "RDY_F_RED";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user1_green {
+ label = "USER1_GREEN";
+ gpios = <&ledgpio 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user1_red {
+ label = "USER1_RED";
+ gpios = <&ledgpio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user2_green {
+ label = "USER2_GREEN";
+ gpios = <&ledgpio 14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user2_red {
+ label = "USER2_RED";
+ gpios = <&ledgpio 15 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "mii";
+ phy-handle = <ðernet_phy>;
+ mac-address = [ 00 00 00 00 00 00 ];
Empty mac? Likely you can just remove it.
+
+ ethernet_phy: emio-phy@2 {
+ reg = <2>;
+ max-speed = <100>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <16>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+ clocks = <&clkc 16>;
+ clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp170-u-boot.dtsi
b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
new file mode 100644
index 00000000000..73c49a7c54c
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include <config.h>
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+ spi_flash: spiflash@0 {
+ bootph-all;
+ };
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+/ {
+ binman {
+ bootph-all;
+ filename = "flash.bin";
+ pad-byte = <0xff>;
+ align-size = <16>;
+ align = <16>;
+
+ blob@0 {
+ filename = "spl/boot.bin";
+ offset = <0x0>;
+ };
+
+ fit {
+ description = "U-Boot BR Zynq boards";
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+
+ images {
+ uboot {
+ description = "U-Boot BR Zynq";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ u-boot-nodtb {
+ };
+ };
+
+ fdt-0 {
+ description = "DTB BR Zynq";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ u-boot-dtb {
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "BR Zynq";
+ firmware = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+
+ blob-ext@0 {
+ filename = "blobs/cfg.img";
+ offset = <0xC0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@5 {
+ filename = "blobs/cfg_opt.img";
+ offset = <0xD0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@1 {
+ bootph-all;
+ filename = "blobs/bitstream.bit";
+ offset = <0x100000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@2 {
+ filename = "blobs/bootar.itb";
+ offset = <0x900000>;
+ size = <0x600000>;
+ optional;
+ };
+
+ blob-ext@3 {
+ filename = "blobs/dtb.bin";
+ offset = <0xF00000>;
+ size = <0x100000>;
+ optional;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp170.dts b/arch/arm/dts/zynq-brcp170.dts
new file mode 100644
index 00000000000..c2856e0d41c
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP170 CPU";
+ compatible = "br,cp170",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_red {
+ label = "RDY_F_RED";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ max-speed = <100>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@58 { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x58>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r.dts b/arch/arm/dts/zynq-brcp1_1r.dts
new file mode 100644
index 00000000000..c78d5b9cfe7
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ max-speed = <1000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r_switch.dts
b/arch/arm/dts/zynq-brcp1_1r_switch.dts
new file mode 100644
index 00000000000..5006a9333dc
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r_switch.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "gmii";
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+ clocks = <&clkc 16>;
+ clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp1_2r.dts b/arch/arm/dts/zynq-brcp1_2r.dts
new file mode 100644
index 00000000000..80e43ff93c6
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_2r.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ max-speed = <1000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
new file mode 100644
index 00000000000..3e1d157abc1
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include <config.h>
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+ spi_flash: spiflash@0 {
+ bootph-all;
+ };
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
+
+/ {
+ binman {
+ bootph-all;
+ filename = "flash.bin";
+ pad-byte = <0xff>;
+ align-size = <16>;
+ align = <16>;
+
+ blob@0 {
+ filename = "spl/boot.bin";
+ offset = <0x0>;
+ };
+
+ fit {
+ description = "U-Boot BR Zynq boards";
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+
+ images {
+ uboot {
+ description = "U-Boot BR Zynq";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ u-boot-nodtb {
+ };
+ };
+
+ fdt-0 {
+ description = "DTB BR Zynq";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ u-boot-dtb {
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "BR Zynq";
+ firmware = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+
+ blob-ext@0 {
+ filename = "blobs/cfg.img";
+ offset = <0xC0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@1 {
+ bootph-all;
+ filename = "blobs/bitstream.bit";
+ offset = <0x100000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@2 {
+ filename = "blobs/bootar.itb";
+ offset = <0x900000>;
+ size = <0x600000>;
+ optional;
+ };
+
+ blob-ext@3 {
+ filename = "blobs/dtb.bin";
+ offset = <0xF00000>;
+ size = <0x100000>;
+ optional;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts
new file mode 100644
index 00000000000..071785c091c
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2.dts
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRSMARC2 CPU";
+ compatible = "br,smarc2",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ can0 = &can0;
+ can1 = &can1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ plk_se_red {
+ label = "PLK_S_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy0>;
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ ethernet_phy0: ethernet-phy@1 {
+ ti,ledcr = <0x0480>;
+ ti,rgmii-rxclk-shift;
+ reg = <1>;
+ };
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy1>;
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ ethernet_phy1: ethernet-phy@3{
+ ti,ledcr = <0x0480>;
+ reg = <3>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ resetc: rststm@60 { /* reset controller */
+ compatible = "bur,rststm";
+ reg = <0x60>;
+ hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>;
+ cooling-min-state = <0>;
+ cooling-max-state = <1>; /* reset gets fired */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&sdhci0 {
+ status = "okay";
+ max-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 265e9ce588a..db20f113232 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -61,5 +61,6 @@ config ZYNQ_SDHCI_MAX_FREQ
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
+source "board/BuR/zynq/Kconfig"
I am fine with this way. My part is pretty much only that wiring and this file
and separation in Makefile works for me.
Thanks,
Michal
