diff --git arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
index 15e880a..f829a6e 100644
--- arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -32,54 +32,55 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pio.h>
+#include <asm/arch-at91/at91sam9263.h>
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
 	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);		/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);		/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	writel(1 << AT91SAM9263_ID_USART0, &pmc->pcer);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
 	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);		/* RXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+	writel(1 << AT91SAM9263_ID_USART1, &pmc->pcer);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
 	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);		/* RXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+	writel(1 << AT91SAM9263_ID_USART2, &pmc->pcer);
 }
 
 void at91_seriald_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
 	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);		/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+	writel(1 << AT91_ID_SYS, &pmc->pcer);
 }
 
 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
 	at91_set_b_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
 	at91_set_b_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
 	at91_set_b_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
 
 	/* Enable clock */
-	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+	writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
@@ -109,14 +110,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* SPI1_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* SPI1_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_SPCK */
 
 	/* Enable clock */
-	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+	writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
@@ -184,7 +185,7 @@ void at91_uhp_hw_init(void)
 #ifdef CONFIG_AT91_CAN
 void at91_can_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
 	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CAN_TX */
 	at91_set_a_periph(AT91_PIO_PORTA, 14, 1);	/* CAN_RX */
diff --git arch/arm/cpu/arm926ejs/at91/clock.c arch/arm/cpu/arm926ejs/at91/clock.c
index 608af2c..cbca88e 100644
--- arch/arm/cpu/arm926ejs/at91/clock.c
+++ arch/arm/cpu/arm926ejs/at91/clock.c
@@ -15,6 +15,7 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91sam9263.h>
 #include <asm/arch/clk.h>
 
 #if !defined(CONFIG_AT91FAMILY)
@@ -145,7 +146,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg)
 int at91_clock_init(unsigned long main_clock)
 {
 	unsigned freq, mckr;
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
 	unsigned tmp;
 	/*
diff --git arch/arm/cpu/arm926ejs/at91/cpu.c arch/arm/cpu/arm926ejs/at91/cpu.c
index c47fb31..df77097 100644
--- arch/arm/cpu/arm926ejs/at91/cpu.c
+++ arch/arm/cpu/arm926ejs/at91/cpu.c
@@ -43,7 +43,7 @@ int arch_cpu_init(void)
 void arch_preboot_os(void)
 {
 	ulong cpiv;
-	at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
+	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
 
 	cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
 
diff --git arch/arm/cpu/arm926ejs/at91/reset.c arch/arm/cpu/arm926ejs/at91/reset.c
index 023719a..22a8cb3 100644
--- arch/arm/cpu/arm926ejs/at91/reset.c
+++ arch/arm/cpu/arm926ejs/at91/reset.c
@@ -30,7 +30,7 @@
 /* Reset the cpu by telling the reset controller to do so */
 void reset_cpu(ulong ignored)
 {
-	at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
+	at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
 
 	writel(AT91_RSTC_KEY
 		| AT91_RSTC_CR_PROCRST	/* Processor Reset */
diff --git arch/arm/cpu/arm926ejs/at91/timer.c arch/arm/cpu/arm926ejs/at91/timer.c
index a087687..9b45785 100644
--- arch/arm/cpu/arm926ejs/at91/timer.c
+++ arch/arm/cpu/arm926ejs/at91/timer.c
@@ -70,11 +70,11 @@ static inline unsigned long long usec_to_tick(unsigned long long usec)
  */
 int timer_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-	at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
 
 	/* Enable PITC Clock */
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+	writel(1 << AT91_ID_SYS, &pmc->pcer);
 
 	/* Enable PITC */
 	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
@@ -90,7 +90,7 @@ int timer_init(void)
  */
 unsigned long long get_ticks(void)
 {
-	at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
+	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
 
 	ulong now = readl(&pit->piir);
 
diff --git arch/arm/include/asm/arch-at91/at91sam9263.h arch/arm/include/asm/arch-at91/at91sam9263.h
index bfd408b..45146b0 100644
--- arch/arm/include/asm/arch-at91/at91sam9263.h
+++ arch/arm/include/asm/arch-at91/at91sam9263.h
@@ -26,112 +26,143 @@
 /*
  * Peripheral identifiers/interrupts.
  */
-#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS	1	/* System Peripherals */
-#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
-#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
-#define ATMEL_ID_PIOCDE	4	/* Parallel IO Controller C, D and E */
+
+#define AT91_ID_FIQ    0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS    1       /* System Peripherals */
+#define AT91_ID_PIOA   2       /* Parallel IO Controller A */
+#define AT91_ID_PIOB   3       /* Parallel IO Controller B */
+#define AT91_ID_PIOCDE 4       /* Parallel IO Controller C, D and E */
+
 /* Reserved:		5 */
 /* Reserved:		6 */
-#define ATMEL_ID_USART0	7	/* USART 0 */
-#define ATMEL_ID_USART1	8	/* USART 1 */
-#define ATMEL_ID_USART2	9	/* USART 2 */
-#define ATMEL_ID_MCI0	10	/* Multimedia Card Interface 0 */
-#define ATMEL_ID_MCI1	11	/* Multimedia Card Interface 1 */
-#define ATMEL_ID_CAN	12	/* CAN */
-#define ATMEL_ID_TWI	13	/* Two-Wire Interface */
-#define ATMEL_ID_SPI0	14	/* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1	15	/* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SSC0	16	/* Serial Synchronous Controller 0 */
-#define ATMEL_ID_SSC1	17	/* Serial Synchronous Controller 1 */
-#define ATMEL_ID_AC97C	18	/* AC97 Controller */
-#define ATMEL_ID_TCB	19	/* Timer Counter 0, 1 and 2 */
-#define ATMEL_ID_PWMC	20	/* Pulse Width Modulation Controller */
-#define ATMEL_ID_EMAC	21	/* Ethernet */
+
+#define  AT91SAM9263_ID_USART0	7	/* USART 0 */
+#define  AT91SAM9263_ID_USART1	8	/* USART 1 */
+#define  AT91SAM9263_ID_USART2	9	/* USART 2 */
+#define  AT91SAM9263_ID_MCI0	10	/* Multimedia Card Interface 0 */
+#define  AT91SAM9263_ID_MCI1	11	/* Multimedia Card Interface 1 */
+#define  AT91SAM9263_ID_CAN	12	/* CAN */
+#define  AT91SAM9263_ID_TWI	13	/* Two-Wire Interface */
+#define  AT91SAM9263_ID_SPI0	14	/* Serial Peripheral Interface 0 */
+#define  AT91SAM9263_ID_SPI1	15	/* Serial Peripheral Interface 1 */
+#define  AT91SAM9263_ID_SSC0	16	/* Serial Synchronous Controller 0 */
+#define  AT91SAM9263_ID_SSC1	17	/* Serial Synchronous Controller 1 */
+#define  AT91SAM9263_ID_AC97C	18	/* AC97 Controller */
+#define  AT91SAM9263_ID_TCB	19	/* Timer Counter 0, 1 and 2 */
+#define  AT91SAM9263_ID_PWMC	20	/* Pulse Width Modulation Controller */
+#define  AT91SAM9263_ID_EMAC	21	/* Ethernet */
+
+
 /* Reserved:		22 */
-#define ATMEL_ID_2DGE	23	/* 2D Graphic Engine */
-#define ATMEL_ID_UDP	24	/* USB Device Port */
-#define ATMEL_ID_ISI	25	/* Image Sensor Interface */
-#define ATMEL_ID_LCDC	26	/* LCD Controller */
-#define ATMEL_ID_DMA	27	/* DMA Controller */
+#define AT91SAM9263_ID_UDP     24      /* USB Device Port */
+#define AT91SAM9263_ID_ISI     25      /* Image Sensor Interface */
+#define AT91SAM9263_ID_LCDC    26      /* LCD Controller */
+#define AT91SAM9263_ID_DMA     27      /* DMA Controller */
+
+
 /* Reserved:		28 */
 #define ATMEL_ID_UHP	29	/* USB Host port */
+#define AT91_ID_IRQ0   30      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91_ID_IRQ1   31      /* Advanced Interrupt Controller (IRQ1) */
+
+
+
 #define ATMEL_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
 #define ATMEL_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
 
 /*
  * User Peripherals physical base addresses.
  */
-#define ATMEL_BASE_UDP		0xfff78000
-#define ATMEL_BASE_TCB0		0xfff7c000
-#define ATMEL_BASE_TC0		0xfff7c000
-#define ATMEL_BASE_TC1		0xfff7c040
-#define ATMEL_BASE_TC2		0xfff7c080
-#define ATMEL_BASE_MCI0		0xfff80000
-#define ATMEL_BASE_MCI1		0xfff84000
-#define ATMEL_BASE_TWI		0xfff88000
-#define ATMEL_BASE_USART0	0xfff8c000
-#define ATMEL_BASE_USART1	0xfff90000
-#define ATMEL_BASE_USART2	0xfff94000
-#define ATMEL_BASE_SSC0		0xfff98000
-#define ATMEL_BASE_SSC1		0xfff9c000
-#define ATMEL_BASE_AC97C	0xfffa0000
-#define ATMEL_BASE_SPI0		0xfffa4000
-#define ATMEL_BASE_SPI1		0xfffa8000
-#define ATMEL_BASE_CAN		0xfffac000
-#define ATMEL_BASE_PWMC		0xfffb8000
-#define ATMEL_BASE_EMAC		0xfffbc000
-#define ATMEL_BASE_ISI		0xfffc4000
-#define ATMEL_BASE_2DGE		0xfffc8000
+
+#define AT91_UDP_BASE          0xfff78000
+#define AT91_TCB0_BASE         0xfff7c000
+#define AT91_TC0_BASE          0xfff7c000
+#define AT91_TC1_BASE          0xfff7c040
+#define AT91_TC2_BASE          0xfff7c080
+#define AT91_MCI0_BASE         0xfff80000
+#define AT91_MCI1_BASE         0xfff84000
+#define AT91_TWI_BASE          0xfff88000
+#define AT91_USART0_BASE       0xfff8c000
+#define AT91_USART1_BASE       0xfff90000
+#define AT91_USART2_BASE       0xfff94000
+#define AT91_SSC0_BASE         0xfff98000
+#define AT91_SSC1_BASE         0xfff9c000
+#define AT91_AC97C_BASE        0xfffa0000
+#define AT91_SPI0_BASE         0xfffa4000
+#define AT91_SPI1_BASE         0xfffa8000
+#define AT91_CAN_BASE          0xfffac000
+#define AT91_PWMC_BASE         0xfffb8000
+#define AT91_EMAC_BASE         0xfffbc000
+#define AT91_ISI_BASE          0xfffc4000
+#define AT91_2DGE_BASE         0xfffc8000
+
+
 
 /*
  * System Peripherals physical base addresses.
  */
-#define ATMEL_BASE_ECC0		0xffffe000
-#define ATMEL_BASE_SDRAMC0	0xffffe200
-#define ATMEL_BASE_SMC0		0xffffe400
-#define ATMEL_BASE_ECC1		0xffffe600
-#define ATMEL_BASE_SDRAMC1	0xffffe800
-#define ATMEL_BASE_SMC1		0xffffea00
-#define ATMEL_BASE_MATRIX	0xffffec00
-#define ATMEL_BASE_CCFG		0xffffed10
-#define ATMEL_BASE_DBGU		0xffffee00
-#define ATMEL_BASE_AIC		0xfffff000
-#define ATMEL_BASE_PIOA		0xfffff200
-#define ATMEL_BASE_PIOB		0xfffff400
-#define ATMEL_BASE_PIOC		0xfffff600
-#define ATMEL_BASE_PIOD		0xfffff800
-#define ATMEL_BASE_PIOE		0xfffffa00
-#define ATMEL_BASE_PMC		0xfffffc00
-#define ATMEL_BASE_RSTC		0xfffffd00
-#define ATMEL_BASE_SHDWC	0xfffffd10
-#define ATMEL_BASE_RTT0		0xfffffd20
-#define ATMEL_BASE_PIT		0xfffffd30
-#define ATMEL_BASE_WDT		0xfffffd40
-#define ATMEL_BASE_RTT1		0xfffffd50
-#define ATMEL_BASE_GPBR		0xfffffd60
+
+#define AT91_ECC0_BASE         0xffffe000
+#define AT91_SDRAMC0_BASE      0xffffe200
+#define AT91_SMC0_BASE         0xffffe400
+#define AT91_ECC1_BASE         0xffffe600
+#define AT91_SDRA_BASEMC1      0xffffe800
+#define AT91_SMC1_BASE         0xffffea00
+#define AT91_MATR_BASEIX       0xffffec00
+#define AT91_CCFG_BASE         0xffffed10
+#define AT91_DBGU_BASE         0xffffee00
+#define AT91_AIC_BASE          0xfffff000
+#define AT91_PIOA_BASE         0xfffff200
+#define AT91_PIOB_BASE         0xfffff400
+#define AT91_PIOC_BASE         0xfffff600
+#define AT91_PIOD_BASE         0xfffff800
+#define AT91_PIOE_BASE         0xfffffa00
+#define AT91_PMC_BASE          0xfffffc00
+#define AT91_RSTC_BASE         0xfffffd00
+#define AT91_SHDW_BASEC                0xfffffd10
+#define AT91_RTT0_BASE         0xfffffd20
+#define AT91_PIT_BASE          0xfffffd30
+#define AT91_WDT_BASE          0xfffffd40
+#define AT91_RTT1_BASE         0xfffffd50
+#define AT91_GPBR_BASE         0xfffffd60
+
+
 
 /*
  * Internal Memory.
  */
-#define ATMEL_BASE_SRAM0	0x00300000	/* Internal SRAM 0 */
 
-#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM */
+#define AT91SAM9263_SRAM0_BASE 0x00300000      /* Internal SRAM 0 base address */
+#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K)    /* Internal SRAM 0 size (80Kb) 
+
+#define AT91SAM9263_ROM_BASE    0x00400000     /* Internal ROM base address */
+#define AT91SAM9263_ROM_SIZE           SZ_128K         /* Internal ROM size (128Kb) */
+
+
 
 #define ATMEL_BASE_SRAM1	0x00500000	/* Internal SRAM 1 */
 
-#define ATMEL_BASE_LCDC		0x00700000	/* LCD Controller */
-#define ATMEL_BASE_DMAC		0x00800000	/* DMA Controller */
-#define ATMEL_BASE_UHP		0x00a00000	/* USB Host controller */
+#define AT91SAM9263_LCDC_BASE  0x00700000      /* LCD Controller */
+#define AT91SAM9263_DMAC_BASE  0x00800000      /* DMA Controller */
+#define AT91_BASE_UHP          0x00a00000      /* USB Host controller */
 
 /*
  * Other misc defines
  */
-#define ATMEL_PIO_PORTS		5		/* this SoCs has 5 PIO */
+
+#define AT91_PIO_PORTS         5               /* this SoCs has 5 PIO */
+#define ATMEL_PMC_UHP          AT91SAM926x_PMC_UHP
+
+/*
+
 
 /*
  * Cpu Name
  */
-#define ATMEL_CPU_NAME		"AT91SAM9263"
+
+#define ATMEL_CPU_NAME          "AT91SAM9263"
+#define AT91_USART_ID           AT91_ID_SYS
+
+#define AT91_MATRIX_BASE     0xffffee00
 
 #endif
diff --git board/atmel/at91sam9263ek/at91sam9263ek.c board/atmel/at91sam9263ek/at91sam9263ek.c
index 91efc07..a915079 100644
--- board/atmel/at91sam9263ek/at91sam9263ek.c
+++ board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -32,7 +32,7 @@
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
@@ -83,7 +83,7 @@ static void at91sam9263ek_nand_hw_init(void)
 		       AT91_SMC_MODE_TDF_CYCLE(2),
 		&smc->cs[3].mode);
 
-	writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE,
+	writel(1 << AT91_ID_PIOA | 1 << AT91_ID_PIOCDE,
 		&pmc->pcer);
 
 	/* Configure RDY/BSY */
@@ -99,7 +99,7 @@ static void at91sam9263ek_macb_hw_init(void)
 {
 	unsigned long 	erstl;
 	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-	at91_pio_t	*pio	= (at91_pio_t *) AT91_PIO_BASE;
+	at91_pio_t	*pio	= (at91_pio_t *) AT91_PIOA_BASE;
 	at91_rstc_t	*rstc	= (at91_rstc_t *) AT91_RSTC_BASE;
 	/* Enable clock */
 	writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
@@ -218,7 +218,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		CONFIG_SYS_AT91_CPU_NAME,
+		ATMEL_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
diff --git board/atmel/at91sam9263ek/led.c board/atmel/at91sam9263ek/led.c
index fa1f05b..560a665 100644
--- board/atmel/at91sam9263ek/led.c
+++ board/atmel/at91sam9263ek/led.c
@@ -27,14 +27,14 @@
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
 
 void coloured_LED_init(void)
 {
 	/* Enable clock */
 	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
-	writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE,
+	writel(1 << AT91_ID_PIOB | 1 << AT91_ID_PIOCDE,
 		&pmc->pcer);
 
 	at91_set_pio_output(CONFIG_RED_LED, 1);
diff --git drivers/gpio/at91_gpio.c drivers/gpio/at91_gpio.c
index be2a026..5657e38 100644
--- drivers/gpio/at91_gpio.c
+++ drivers/gpio/at91_gpio.c
@@ -29,7 +29,7 @@
  *
  * As the code is right now, it expects all PIO ports A,B,C,...
  * to be evenly spaced in the memory map:
- * ATMEL_BASE_PIOA + port * sizeof at91pio_t
+ * AT91_PIOA_BASE + port * sizeof at91pio_t
  * This might not necessaryly be true in future Atmel SoCs.
  * This code should be fixed to use a pointer array to the ports.
  */
@@ -43,7 +43,7 @@
 
 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
 {
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
@@ -62,7 +62,7 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
  */
 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
 {
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
@@ -79,7 +79,7 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
  */
 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
 {
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
@@ -97,7 +97,7 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
  */
 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
 {
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
@@ -116,7 +116,7 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
  */
 int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
 {
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
@@ -135,7 +135,7 @@ int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
  */
 int at91_set_pio_output(unsigned port, u32 pin, int value)
 {
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
@@ -157,7 +157,7 @@ int at91_set_pio_output(unsigned port, u32 pin, int value)
  */
 int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
 {
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
@@ -176,7 +176,7 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
  */
 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
 {
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
@@ -194,7 +194,7 @@ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
  */
 int at91_set_pio_value(unsigned port, unsigned pin, int value)
 {
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
@@ -213,7 +213,7 @@ int at91_set_pio_value(unsigned port, unsigned pin, int value)
 int at91_get_pio_value(unsigned port, unsigned pin)
 {
 	u32		pdsr = 0;
-	at91_pio_t	*pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+	at91_pio_t	*pio = (at91_pio_t *) AT91_PIOA_BASE;
 	u32		mask;
 
 	if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
diff --git drivers/spi/atmel_dataflash_spi.c drivers/spi/atmel_dataflash_spi.c
index 9c991e8..c7174b1 100644
--- drivers/spi/atmel_dataflash_spi.c
+++ drivers/spi/atmel_dataflash_spi.c
@@ -49,18 +49,18 @@
 void AT91F_SpiInit(void)
 {
 	/* Reset the SPI */
-	writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR);
+	writel(AT91_SPI_SWRST, AT91_SPI0_BASE + AT91_SPI_CR);
 
 	/* Configure SPI in Master Mode with No CS selected !!! */
 	writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
-	       ATMEL_BASE_SPI0 + AT91_SPI_MR);
+	       AT91_SPI0_BASE + AT91_SPI_MR);
 
 	/* Configure CS0 */
 	writel(AT91_SPI_NCPHA |
 	       (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
 	       (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
 	       ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
-	       ATMEL_BASE_SPI0 + AT91_SPI_CSR(0));
+	       AT91_SPI0_BASE + AT91_SPI_CSR(0));
 
 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
 	/* Configure CS1 */
@@ -68,7 +68,7 @@ void AT91F_SpiInit(void)
 	       (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
 	       (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
 	       ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
-	       ATMEL_BASE_SPI0 + AT91_SPI_CSR(1));
+	       AT91_SPI0_BASE + AT91_SPI_CSR(1));
 #endif
 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
 	/* Configure CS2 */
@@ -76,7 +76,7 @@ void AT91F_SpiInit(void)
 	       (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
 	       (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
 	       ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
-	       ATMEL_BASE_SPI0 + AT91_SPI_CSR(2));
+	       AT91_SPI0_BASE + AT91_SPI_CSR(2));
 #endif
 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
 	/* Configure CS3 */
@@ -84,13 +84,13 @@ void AT91F_SpiInit(void)
 	       (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
 	       (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
 	       ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
-	       ATMEL_BASE_SPI0 + AT91_SPI_CSR(3));
+	       AT91_SPI0_BASE + AT91_SPI_CSR(3));
 #endif
 
 	/* SPI_Enable */
-	writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
+	writel(AT91_SPI_SPIEN, AT91_SPI0_BASE + AT91_SPI_CR);
 
-	while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS))
+	while (!(readl(AT91_SPI0_BASE + AT91_SPI_SR) & AT91_SPI_SPIENS))
 		;
 
 	/*
@@ -98,8 +98,8 @@ void AT91F_SpiInit(void)
 	 * Should not be needed for new silicon (Rev B)
 	 */
 	udelay(500000);
-	readl(ATMEL_BASE_SPI0 + AT91_SPI_SR);
-	readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR);
+	readl(AT91_SPI0_BASE + AT91_SPI_SR);
+	readl(AT91_SPI0_BASE + AT91_SPI_RDR);
 
 }
 
@@ -109,33 +109,33 @@ void AT91F_SpiEnable(int cs)
 
 	switch (cs) {
 	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
-		mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
+		mode = readl(AT91_SPI0_BASE + AT91_SPI_MR);
 		mode &= 0xFFF0FFFF;
 		writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
-		       ATMEL_BASE_SPI0 + AT91_SPI_MR);
+		       AT91_SPI0_BASE + AT91_SPI_MR);
 		break;
 	case 1:	/* Configure SPI CS1 for Serial DataFlash AT45DBxx */
-		mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
+		mode = readl(AT91_SPI0_BASE + AT91_SPI_MR);
 		mode &= 0xFFF0FFFF;
 		writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
-		       ATMEL_BASE_SPI0 + AT91_SPI_MR);
+		       AT91_SPI0_BASE + AT91_SPI_MR);
 		break;
 	case 2:	/* Configure SPI CS2 for Serial DataFlash AT45DBxx */
-		mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
+		mode = readl(AT91_SPI0_BASE + AT91_SPI_MR);
 		mode &= 0xFFF0FFFF;
 		writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
-		       ATMEL_BASE_SPI0 + AT91_SPI_MR);
+		       AT91_SPI0_BASE + AT91_SPI_MR);
 		break;
 	case 3:
-		mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
+		mode = readl(AT91_SPI0_BASE + AT91_SPI_MR);
 		mode &= 0xFFF0FFFF;
 		writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
-		       ATMEL_BASE_SPI0 + AT91_SPI_MR);
+		       AT91_SPI0_BASE + AT91_SPI_MR);
 		break;
 	}
 
 	/* SPI_Enable */
-	writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
+	writel(AT91_SPI_SPIEN, AT91_SPI0_BASE + AT91_SPI_CR);
 }
 
 unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
@@ -148,30 +148,30 @@ unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
 	pDesc->state = BUSY;
 
 	writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
-		ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
+		AT91_SPI0_BASE + AT91_SPI_PTCR);
 
 	/* Initialize the Transmit and Receive Pointer */
 	writel((unsigned int)pDesc->rx_cmd_pt,
-		ATMEL_BASE_SPI0 + AT91_SPI_RPR);
+		AT91_SPI0_BASE + AT91_SPI_RPR);
 	writel((unsigned int)pDesc->tx_cmd_pt,
-		ATMEL_BASE_SPI0 + AT91_SPI_TPR);
+		AT91_SPI0_BASE + AT91_SPI_TPR);
 
 	/* Intialize the Transmit and Receive Counters */
-	writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR);
-	writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR);
+	writel(pDesc->rx_cmd_size, AT91_SPI0_BASE + AT91_SPI_RCR);
+	writel(pDesc->tx_cmd_size, AT91_SPI0_BASE + AT91_SPI_TCR);
 
 	if (pDesc->tx_data_size != 0) {
 		/* Initialize the Next Transmit and Next Receive Pointer */
 		writel((unsigned int)pDesc->rx_data_pt,
-			ATMEL_BASE_SPI0 + AT91_SPI_RNPR);
+			AT91_SPI0_BASE + AT91_SPI_RNPR);
 		writel((unsigned int)pDesc->tx_data_pt,
-			ATMEL_BASE_SPI0 + AT91_SPI_TNPR);
+			AT91_SPI0_BASE + AT91_SPI_TNPR);
 
 		/* Intialize the Next Transmit and Next Receive Counters */
 		writel(pDesc->rx_data_size,
-			ATMEL_BASE_SPI0 + AT91_SPI_RNCR);
+			AT91_SPI0_BASE + AT91_SPI_RNCR);
 		writel(pDesc->tx_data_size,
-			ATMEL_BASE_SPI0 + AT91_SPI_TNCR);
+			AT91_SPI0_BASE + AT91_SPI_TNCR);
 	}
 
 	/* arm simple, non interrupt dependent timer */
@@ -179,12 +179,12 @@ unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
 	timeout = 0;
 
 	writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN,
-		ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
-	while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
+		AT91_SPI0_BASE + AT91_SPI_PTCR);
+	while (!(readl(AT91_SPI0_BASE + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
 		((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT))
 		;
 	writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
-		ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
+		AT91_SPI0_BASE + AT91_SPI_PTCR);
 	pDesc->state = IDLE;
 
 	if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
diff --git drivers/spi/atmel_spi.c drivers/spi/atmel_spi.c
index 33e38b6..1b1338f 100644
--- drivers/spi/atmel_spi.c
+++ drivers/spi/atmel_spi.c
@@ -27,7 +27,6 @@
 
 #include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
-
 #include "atmel_spi.h"
 
 void spi_init()
diff --git drivers/usb/host/ohci-at91.c drivers/usb/host/ohci-at91.c
index 9532dd9..630656d 100644
--- drivers/usb/host/ohci-at91.c
+++ drivers/usb/host/ohci-at91.c
@@ -32,7 +32,7 @@
 
 int usb_cpu_init(void)
 {
-	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
+	at91_pmc_t *pmc	= (at91_pmc_t *)AT91_PMC_BASE;
 
 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
     defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
@@ -65,7 +65,7 @@ int usb_cpu_init(void)
 
 int usb_cpu_stop(void)
 {
-	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
+	at91_pmc_t *pmc	= (at91_pmc_t *)AT91_PMC_BASE;
 
 	/* Disable USB host clock. */
 	writel(1 << ATMEL_ID_UHP, &pmc->pcdr);
diff --git include/configs/at91sam9263ek.h include/configs/at91sam9263ek.h
index f6cb406..f2b28cd 100644
--- include/configs/at91sam9263ek.h
+++ include/configs/at91sam9263ek.h
@@ -27,6 +27,14 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define ATMEL_PIO_PORTS         5
+#define CONFIG_SYS_AT91_SLOW_CLOCK   32768 
+#define CONFIG_AT91FAMILY 	1
+#define CONFIG_SYS_SDRAM_BASE                0x20000000
+#define CONFIG_SYS_INIT_SP_ADDR              (CONFIG_SYS_SDRAM_BASE + 0x1000 - - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_AT91_LEGACY     1 
+#define ATMEL_PMC_UHP          AT91SAM926x_PMC_UHP
+
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	16367660	/* 16.367 MHz crystal */
 #define CONFIG_SYS_HZ		1000
@@ -49,6 +57,8 @@
  * Hardware drivers
  */
 #define CONFIG_AT91_GPIO	1
+#define CONFIG_USART_BASE   AT91_USART1_BASE
+#define	CONFIG_USART_ID	     AT91_ID_SYS
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1