The ENETCv4 port DT nodes on i.MX95 may contain optional clock phandle
to IMX95_CLK_ENETREF "ref" clock. These "ref" clock must be enabled for
the ethernet to work. These "ref" clock are enabled after cold boot, but
when the system booted Linux and rebooted, those "ref" clock might have
been disabled in the process, which would make ethernet inoperable after
reboot. Make sure those "ref" clock are always correctly enabled.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: Alice Guo <alice....@nxp.com>
Cc: Fabio Estevam <feste...@denx.de>
Cc: Joe Hershberger <joe.hershber...@ni.com>
Cc: Ramon Fried <rfried....@gmail.com>
Cc: Tim Harvey <thar...@gateworks.com>
Cc: Tom Rini <tr...@konsulko.com>
Cc: Ye Li <ye...@nxp.com>
Cc: u-boot@lists.denx.de
---
drivers/net/fsl_enetc.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index 67ef5f34a8a..52fa820f518 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -5,6 +5,7 @@
* Copyright 2023-2025 NXP
*/
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <fdt_support.h>
@@ -981,11 +982,31 @@ static const struct eth_ops enetc_ops_imx = {
.read_rom_hwaddr = enetc_read_rom_hwaddr,
};
+static int enetc_probe_imx(struct udevice *dev)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "ref");
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ ret = clk_enable(clk);
+ if (ret)
+ return ret;
+
+ ret = enetc_probe(dev);
+ if (ret)
+ clk_disable(clk);
+
+ return ret;
+}
+
U_BOOT_DRIVER(eth_enetc_imx) = {
.name = ENETC_DRIVER_NAME,
.id = UCLASS_ETH,
.bind = enetc_bind,
- .probe = enetc_probe,
+ .probe = enetc_probe_imx,
.remove = enetc_remove,
.ops = &enetc_ops_imx,
.priv_auto = sizeof(struct enetc_priv),
--
2.45.2
