Am 05/21/2011 02:06 AM, schrieb Marek Vasut: > >> + /* Setup GPIO's for 33MHz clock output */ >> + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); >> + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); >> + writel(0x01FF01FF, IXP425_GPIO_GPCLKR); >> + >> + /* turn off all LEDs */ >> + writew(0x0000, DVLHOST_LED_LATCH); >> + >> + udelay(533); > Why 533 ? > >> + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST);
Hm - that is copied from the PCI init sequence in pci_ixp.c - however, the constant *does* look dodgy: We need at least 100us reset pulse *after the clock is stable* - whatever time that requires. On the other hand, the PCI spec requires 2^25 clocks after reset before the first configuration access, which would be around 1s - we probably violate that, since the timing depends on what other code delays operation until the first PCI configuration access. Since PCI is not 100% functional (at least in my attempts), even on the existing IXDP425 board, I would like to leave this as is for now - at least it is consistent across all IXP boards. cu Michael _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
