On Mon, Dec 30, 2024 at 03:03:39PM +0530, Kumar, Udit wrote:
> Hello Venkatesh,
>
> On 12/30/2024 12:32 PM, Venkatesh Yadav Abbarapu wrote:
> > Update the spi_nor_read() function based on the config SPI_FLASH_BAR
> > and update the length and bank calculation by spliting the memory of
> > 16MB size banks only when the address width is 3byte.
> > Fix the read issue for 4byte address width by passing the entire
> > length to the read function.
> >
> > Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories
> > support")
> > Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbar...@amd.com>
> > ---
> > Changes in v2:
> > - Update the nor read for parallel configuration and for other case
> > keep the code as is.
> > - Fixed the commit description.
> > - Tested the changes with s25fl128s flash Zynq> sf probe 0 0 0
> > SF: Detected s25fl128s with page size 256 Bytes, erase size 64 KiB,
> > total 16 MiB Zynq> time sf erase 0x0 0x1000000;mw.b 0x8000 aabbccdd
> > 0x1000000;time Zynq> sf write 0x8000 0x0 0x1000000;mw.b 0x8008000 0x0
> > 0x1000000;time Zynq> sf read 0x8008000 0x0 0x1000000;cmp.b 0x8000
> > 0x8008000 0x1000000
> > SF: 16777216 bytes @ 0x0 Erased: OK
> >
> > time: 32.464 seconds
> > device 0 whole chip
> > SF: 16777216 bytes @ 0x0 Written: OK
> >
> > time: 15.515 seconds
> > device 0 whole chip
> > SF: 16777216 bytes @ 0x0 Read: OK
> >
> > time: 1.557 seconds
> > Total of 16777216 byte(s) were the same
> >
> > Changes in v3:
> > - Compile out the parallel code in spi_nor_erase() if the
> > SPI_STACKED_PARALLEL
> > is enabled.
> >
> > Changes in v4:
> > - Update the bank calculation only when SPL_FLASH_BAR is enabled.
> >
> > Changes in v5:
> > - Update the parallel code in the spi_nor_read() only if the
> > SPI_STACKED_PARALLEL
> > config is enabled.
> >
> > Changes in v6:
> > - Remove the hardcoded address width for 4byte.
> > - Move the length condition with rem_bank_len under SPI_FLASH_BAR flag.
> > ---
> > drivers/mtd/spi/spi-nor-core.c | 75 ++++++++++++++++++++--------------
> > 1 file changed, 44 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> > index ec841fb13bd..6f352c5c0e2 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -1130,17 +1130,19 @@ static int spi_nor_erase(struct mtd_info *mtd,
> > struct erase_info *instr)
> > goto erase_err;
> > }
> > offset = addr;
> > - if (nor->flags & SNOR_F_HAS_PARALLEL)
> > - offset /= 2;
> > -
> > - if (nor->flags & SNOR_F_HAS_STACKED) {
> > - if (offset >= (mtd->size / 2))
> > - nor->spi->flags |= SPI_XFER_U_PAGE;
> > - else
> > - nor->spi->flags &= ~SPI_XFER_U_PAGE;
> > + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) {
> > + if (nor->flags & SNOR_F_HAS_PARALLEL)
> > + offset /= 2;
> > +
> > + if (nor->flags & SNOR_F_HAS_STACKED) {
> > + if (offset >= (mtd->size / 2))
> > + nor->spi->flags |= SPI_XFER_U_PAGE;
> > + else
> > + nor->spi->flags &= ~SPI_XFER_U_PAGE;
> > + }
>
> I believe SNOR_F_HAS_PARALLEL and SNOR_F_HAS_STACKED flags are specific to
> your use case.
>
> which should be set if flash is parallel and/or stacked, then why you want
> to protect with another
>
> if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL).Because at this point in the release cycle I really really want these isolated from the rest of the code paths, given the problems we've seen. I expect some cleanups for v2025.04 that will get wider testing than happened for what will be in v2025.01. -- Tom
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