Rervision A33-Vstar is an evaluation board for their A33-Core1 A33-based
SoM.

Add support for it.

Fastboot support is enabled for flashing the eMMC included within the
SoM, and R8152 Ethernet is enabled for the evaluation board's onboard
USB-to-Ethernet.

The device tree files are from Linux v6.13-rc1, with PMIC interrupt
patched to match the r_intc node in U-Boot.

Signed-off-by: Icenowy Zheng <u...@icenowy.me>
---
 arch/arm/dts/Makefile                   |   1 +
 arch/arm/dts/sun8i-a33-vstar-core1.dtsi |  96 +++++++++++
 arch/arm/dts/sun8i-a33-vstar.dts        | 205 ++++++++++++++++++++++++
 board/sunxi/MAINTAINERS                 |   5 +
 configs/A33-Vstar_defconfig             |  23 +++
 5 files changed, 330 insertions(+)
 create mode 100644 arch/arm/dts/sun8i-a33-vstar-core1.dtsi
 create mode 100644 arch/arm/dts/sun8i-a33-vstar.dts
 create mode 100644 configs/A33-Vstar_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6ad59aeed5f..55dde416d71 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -654,6 +654,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
        sun8i-a33-olinuxino.dtb \
        sun8i-a33-q8-tablet.dtb \
        sun8i-a33-sinlinx-sina33.dtb \
+       sun8i-a33-vstar.dtb \
        sun8i-r16-bananapi-m2m.dtb \
        sun8i-r16-nintendo-nes-classic.dtb \
        sun8i-r16-nintendo-super-nes-classic.dtb \
diff --git a/arch/arm/dts/sun8i-a33-vstar-core1.dtsi 
b/arch/arm/dts/sun8i-a33-vstar-core1.dtsi
new file mode 100644
index 00000000000..5b7057015cc
--- /dev/null
+++ b/arch/arm/dts/sun8i-a33-vstar-core1.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Icenowy Zheng <u...@icenowy.me>
+ */
+
+#include "sun8i-a33.dtsi"
+
+&mmc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc2_8bit_pins>;
+       vmmc-supply = <&reg_dcdc1>;
+       bus-width = <8>;
+       non-removable;
+       cap-mmc-hw-reset;
+       status = "okay";
+};
+
+&mmc2_8bit_pins {
+       /* Increase drive strength for DDR modes */
+       drive-strength = <40>;
+};
+
+&r_rsb {
+       status = "okay";
+
+       axp22x: pmic@3a3 {
+               compatible = "x-powers,axp223";
+               reg = <0x3a3>;
+               interrupt-parent = <&r_intc>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               eldoin-supply = <&reg_dcdc1>;
+               x-powers,drive-vbus-en;
+       };
+};
+
+#include "axp223.dtsi"
+
+&reg_aldo1 {
+       regulator-always-on;
+       regulator-min-microvolt = <3300000>;
+       regulator-max-microvolt = <3300000>;
+       regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+       regulator-always-on;
+       regulator-min-microvolt = <2350000>;
+       regulator-max-microvolt = <2650000>;
+       regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+       regulator-always-on;
+       regulator-min-microvolt = <3300000>;
+       regulator-max-microvolt = <3300000>;
+       regulator-name = "vcc-avcc";
+};
+
+&reg_dc5ldo {
+       regulator-always-on;
+       regulator-min-microvolt = <900000>;
+       regulator-max-microvolt = <1400000>;
+       regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+       regulator-always-on;
+       regulator-min-microvolt = <3300000>;
+       regulator-max-microvolt = <3300000>;
+       regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+       regulator-always-on;
+       regulator-min-microvolt = <900000>;
+       regulator-max-microvolt = <1400000>;
+       regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+       regulator-always-on;
+       regulator-min-microvolt = <900000>;
+       regulator-max-microvolt = <1400000>;
+       regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+       regulator-always-on;
+       regulator-min-microvolt = <1500000>;
+       regulator-max-microvolt = <1500000>;
+       regulator-name = "vcc-dram";
+};
+
+&reg_rtc_ldo {
+       regulator-name = "vcc-rtc";
+};
diff --git a/arch/arm/dts/sun8i-a33-vstar.dts b/arch/arm/dts/sun8i-a33-vstar.dts
new file mode 100644
index 00000000000..9f5c29b3df4
--- /dev/null
+++ b/arch/arm/dts/sun8i-a33-vstar.dts
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Icenowy Zheng <u...@icenowy.me>
+ */
+
+/dts-v1/;
+#include "sun8i-a33-vstar-core1.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "Rervision A33-Vstar";
+       compatible = "rervision,a33-vstar",
+                    "rervision,a33-core1",
+                    "allwinner,sun8i-a33";
+
+       aliases {
+               serial0 = &uart0;
+               ethernet0 = &r8152;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       reg_usb1_vbus: regulator-usb1-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usb1-vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+               enable-active-high;
+               gpio = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
+       };
+
+       wifi_pwrseq: pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
+               clocks = <&rtc CLK_OSC32K_FANOUT>;
+               clock-names = "ext_clock";
+       };
+};
+
+&ac_power_supply {
+       status = "okay";
+};
+
+&codec {
+       status = "okay";
+};
+
+&dai {
+       status = "okay";
+};
+
+&ehci0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       hub@1 {
+               /* Onboard GL850G hub which needs no extra power sequence */
+               compatible = "usb5e3,608";
+               reg = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               r8152: ethernet@4 {
+                       /*
+                        * Onboard Realtek RTL8152 USB Ethernet,
+                        * with no MAC address programmed
+                        */
+                       compatible = "usbbda,8152";
+                       reg = <4>;
+               };
+       };
+};
+
+&lradc {
+       vref-supply = <&reg_aldo3>;
+       status = "okay";
+
+       button-191 {
+               label = "V+";
+               linux,code = <KEY_VOLUMEUP>;
+               channel = <0>;
+               voltage = <191011>;
+       };
+
+       button-391 {
+               label = "V-";
+               linux,code = <KEY_VOLUMEDOWN>;
+               channel = <0>;
+               voltage = <391304>;
+       };
+
+       button-600 {
+               label = "BACK";
+               linux,code = <KEY_BACK>;
+               channel = <0>;
+               voltage = <600000>;
+       };
+};
+
+&mmc0 {
+       vmmc-supply = <&reg_dcdc1>;
+       bus-width = <4>;
+       cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
+       status = "okay";
+};
+
+&mmc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc1_pg_pins>;
+       vmmc-supply = <&reg_dldo1>;
+       mmc-pwrseq = <&wifi_pwrseq>;
+       bus-width = <4>;
+       non-removable;
+       status = "okay";
+
+       brcmf: wifi@1 {
+               reg = <1>;
+               compatible = "brcm,bcm4329-fmac";
+               interrupt-parent = <&r_pio>;
+               interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+               interrupt-names = "host-wake";
+       };
+};
+
+/*
+ * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same
+ * time, with the two being in sync. Since this is not really
+ * supported right now, just use the two as always on, and we will fix
+ * it later.
+ */
+&reg_dldo1 {
+       regulator-always-on;
+       regulator-min-microvolt = <3300000>;
+       regulator-max-microvolt = <3300000>;
+       regulator-name = "vcc-wifi0";
+};
+
+&reg_dldo2 {
+       regulator-always-on;
+       regulator-min-microvolt = <3300000>;
+       regulator-max-microvolt = <3300000>;
+       regulator-name = "vcc-wifi1";
+};
+
+&reg_drivevbus {
+       regulator-name = "usb0-vbus";
+       status = "okay";
+};
+
+&sound {
+       /* TODO: on-board microphone */
+
+       simple-audio-card,widgets = "Headphone", "Headphone Jack";
+       simple-audio-card,routing =
+               "Left DAC", "DACL",
+               "Right DAC", "DACR",
+               "Headphone Jack", "HP";
+       status = "okay";
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pb_pins>;
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
+       uart-has-rtscts;
+       status = "okay";
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               clocks = <&rtc CLK_OSC32K_FANOUT>;
+               clock-names = "lpo";
+               vbat-supply = <&reg_dldo1>;
+               device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+               host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+               shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+       };
+};
+
+&usb_otg {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&usb_power_supply {
+       status = "okay";
+};
+
+&usbphy {
+       usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+       usb0_vbus_power-supply = <&usb_power_supply>;
+       usb0_vbus-supply = <&reg_drivevbus>;
+       usb1_vbus-supply = <&reg_usb1_vbus>;
+       status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 84799879e85..5592d366600 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -526,6 +526,11 @@ M: Quentin Schulz <quentin.sch...@free-electrons.com>
 S:     Maintained
 F:     configs/parrot_r16_defconfig
 
+RERVISION A33-VSTAR BOARD
+M:     Icenowy Zheng <u...@icenowy.me>
+S:     Maintained
+F:     configs/A33-Vstar_defconfig
+
 SINLINX SINA31s BOARD
 M:     Chen-Yu Tsai <w...@csie.org>
 S:     Maintained
diff --git a/configs/A33-Vstar_defconfig b/configs/A33-Vstar_defconfig
new file mode 100644
index 00000000000..0053c243444
--- /dev/null
+++ b/configs/A33-Vstar_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-vstar"
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=15291
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_USB1_VBUS_PIN="PB2"
+# CONFIG_VIDEO_SUNXI is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CMD_DFU=y
+CONFIG_DFU_RAM=y
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_AXP_DCDC1_VOLT=3300
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_USB_ETHER is not set
-- 
2.47.1

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