нд, 1 груд. 2024 р. о 17:20 Marek Vasut <ma...@denx.de> пише: > > On 12/1/24 4:05 PM, Svyatoslav Ryhel wrote: > > [...] > > >> @@ -288,7 +289,8 @@ static int dm_test_power_regulator_autoset(struct > >> unit_test_state *uts) > >> * Expected output state: uV=1200000; uA=200000; output enabled > >> */ > >> platname = regulator_names[BUCK1][PLATNAME]; > >> - ut_asserteq(-EALREADY, regulator_autoset_by_name(platname, > >> &dev_autoset)); > >> + ut_asserteq(-EALREADY, > >> + regulator_autoset_by_name(platname, &dev_autoset)); > >> > >> /* Check, that the returned device is proper */ > >> ut_assertok(regulator_get_by_platname(platname, &dev)); > >> -- > >> 2.43.0 > >> > > > > It seems that I have found a fix for this issue. Simon, please test > > this commit > > https://gitlab.com/clamor-s/u-boot/-/commit/6149722aa48f84d9ea037ae990141a231106244e > > So this regulator problem was a tegra platform specific issue after all. > > Nice find, thanks !
Not a tegra specific but rather timing of calls. Regulator autoprobe was called from board after clock setup but with your change regulator probe now is much much earlier. This may cause disruptions on other platforms as well.
