This code is getting a bit complicated, split it out to try and keep
things a bit better organised as we're going to be supporting populating
the memory layout from various other sources.
Signed-off-by: Caleb Connolly <caleb.conno...@linaro.org>
---
arch/arm/mach-snapdragon/Makefile | 2 +-
arch/arm/mach-snapdragon/board.c | 94 ----------------------------
arch/arm/mach-snapdragon/dram.c | 116 +++++++++++++++++++++++++++++++++++
arch/arm/mach-snapdragon/qcom-priv.h | 2 +
4 files changed, 119 insertions(+), 95 deletions(-)
diff --git a/arch/arm/mach-snapdragon/Makefile
b/arch/arm/mach-snapdragon/Makefile
index 343e825c6fdd..e481e4f26e5c 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikow...@gmail.com>
-obj-y += board.o
+obj-y += board.o dram.o
obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += capsule_update.o
obj-$(CONFIG_OF_LIVE) += of_fixup.o
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 75a880f093ca..8d171957b852 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -40,102 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
struct mm_region *mem_map = rbx_mem_map;
-static struct {
- phys_addr_t start;
- phys_size_t size;
-} prevbl_ddr_banks[CONFIG_NR_DRAM_BANKS] __section(".data") = { 0 };
-
-int dram_init(void)
-{
- /*
- * gd->ram_base / ram_size have been setup already
- * in qcom_parse_memory().
- */
- return 0;
-}
-
-static int ddr_bank_cmp(const void *v1, const void *v2)
-{
- const struct {
- phys_addr_t start;
- phys_size_t size;
- } *res1 = v1, *res2 = v2;
-
- if (!res1->size)
- return 1;
- if (!res2->size)
- return -1;
-
- return (res1->start >> 24) - (res2->start >> 24);
-}
-
-/* This has to be done post-relocation since gd->bd isn't preserved */
-static void qcom_configure_bi_dram(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start;
- gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size;
- }
-}
-
-int dram_init_banksize(void)
-{
- qcom_configure_bi_dram();
-
- return 0;
-}
-
-static void qcom_parse_memory(void)
-{
- ofnode node;
- const fdt64_t *memory;
- int memsize;
- phys_addr_t ram_end = 0;
- int i, j, banks;
-
- node = ofnode_path("/memory");
- if (!ofnode_valid(node)) {
- log_err("No memory node found in device tree!\n");
- return;
- }
- memory = ofnode_read_prop(node, "reg", &memsize);
- if (!memory) {
- log_err("No memory configuration was provided by the previous
bootloader!\n");
- return;
- }
-
- banks = min(memsize / (2 * sizeof(u64)), (ulong)CONFIG_NR_DRAM_BANKS);
-
- if (memsize / sizeof(u64) > CONFIG_NR_DRAM_BANKS * 2)
- log_err("Provided more than the max of %d memory banks\n",
CONFIG_NR_DRAM_BANKS);
-
- if (banks > CONFIG_NR_DRAM_BANKS)
- log_err("Provided more memory banks than we can handle\n");
-
- for (i = 0, j = 0; i < banks * 2; i += 2, j++) {
- prevbl_ddr_banks[j].start = get_unaligned_be64(&memory[i]);
- prevbl_ddr_banks[j].size = get_unaligned_be64(&memory[i + 1]);
- /* SM8650 boards sometimes have empty regions! */
- if (!prevbl_ddr_banks[j].size) {
- j--;
- continue;
- }
- ram_end = max(ram_end, prevbl_ddr_banks[j].start +
prevbl_ddr_banks[j].size);
- }
-
- /* Sort our RAM banks -_- */
- qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]),
ddr_bank_cmp);
-
- gd->ram_base = prevbl_ddr_banks[0].start;
- gd->ram_size = ram_end - gd->ram_base;
- debug("ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n",
- gd->ram_base, gd->ram_size, ram_end);
-}
-
static void show_psci_version(void)
{
struct arm_smccc_res res;
diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c
new file mode 100644
index 000000000000..c4c60039cb4c
--- /dev/null
+++ b/arch/arm/mach-snapdragon/dram.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Memory layout parsing for Qualcomm.
+ */
+
+#define LOG_CATEGORY LOGC_BOARD
+#define pr_fmt(fmt) "QCOM-DRAM: " fmt
+
+#include <asm-generic/unaligned.h>
+#include <dm.h>
+#include <log.h>
+#include <sort.h>
+
+static struct {
+ phys_addr_t start;
+ phys_size_t size;
+} prevbl_ddr_banks[CONFIG_NR_DRAM_BANKS] __section(".data") = { 0 };
+
+int dram_init(void)
+{
+ /*
+ * gd->ram_base / ram_size have been setup already
+ * in qcom_parse_memory().
+ */
+ return 0;
+}
+
+static int ddr_bank_cmp(const void *v1, const void *v2)
+{
+ const struct {
+ phys_addr_t start;
+ phys_size_t size;
+ } *res1 = v1, *res2 = v2;
+
+ if (!res1->size)
+ return 1;
+ if (!res2->size)
+ return -1;
+
+ return (res1->start >> 24) - (res2->start >> 24);
+}
+
+/* This has to be done post-relocation since gd->bd isn't preserved */
+static void qcom_configure_bi_dram(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start;
+ gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size;
+ }
+}
+
+int dram_init_banksize(void)
+{
+ qcom_configure_bi_dram();
+
+ return 0;
+}
+
+static void qcom_parse_memory_dt(const fdt64_t *memory, int banks, phys_addr_t
*ram_end)
+{
+ int i, j;
+
+ if (banks > CONFIG_NR_DRAM_BANKS)
+ log_err("Provided more memory banks than we can handle\n");
+
+ for (i = 0, j = 0; i < banks * 2; i += 2, j++) {
+ prevbl_ddr_banks[j].start = get_unaligned_be64(&memory[i]);
+ prevbl_ddr_banks[j].size = get_unaligned_be64(&memory[i + 1]);
+ /* SM8650 boards sometimes have empty regions! */
+ if (!prevbl_ddr_banks[j].size) {
+ j--;
+ continue;
+ }
+ *ram_end = max(*ram_end, prevbl_ddr_banks[j].start +
prevbl_ddr_banks[j].size);
+ }
+}
+
+/* Parse the memory layout from the FDT. */
+void qcom_parse_memory(void)
+{
+ ofnode node;
+ const fdt64_t *memory;
+ int memsize;
+ phys_addr_t ram_end = 0;
+ int banks;
+
+ node = ofnode_path("/memory");
+ if (!ofnode_valid(node)) {
+ log_err("No memory node found in device tree!\n");
+ return;
+ }
+ memory = ofnode_read_prop(node, "reg", &memsize);
+ if (!memory) {
+ log_err("No memory configuration was provided by the previous
bootloader!\n");
+ return;
+ }
+
+ banks = min(memsize / (2 * sizeof(u64)), (ulong)CONFIG_NR_DRAM_BANKS);
+
+ if (memsize / sizeof(u64) > CONFIG_NR_DRAM_BANKS * 2)
+ log_err("Provided more than the max of %d memory banks\n",
CONFIG_NR_DRAM_BANKS);
+
+ qcom_parse_memory_dt(memory, banks, &ram_end);
+
+ debug("%d banks, ram_base = %#011lx, ram_size = %#011llx, ram_end =
%#011llx\n",
+ banks, gd->ram_base, gd->ram_size, ram_end);
+ /* Sort our RAM banks -_- */
+ qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]),
ddr_bank_cmp);
+
+ gd->ram_base = prevbl_ddr_banks[0].start;
+ gd->ram_size = ram_end - gd->ram_base;
+ debug("%d banks, ram_base = %#011lx, ram_size = %#011llx, ram_end =
%#011llx\n",
+ banks, gd->ram_base, gd->ram_size, ram_end);
+}
diff --git a/arch/arm/mach-snapdragon/qcom-priv.h
b/arch/arm/mach-snapdragon/qcom-priv.h
index 74d39197b89f..b7f3bf798d3c 100644
--- a/arch/arm/mach-snapdragon/qcom-priv.h
+++ b/arch/arm/mach-snapdragon/qcom-priv.h
@@ -22,5 +22,7 @@ static inline void qcom_of_fixup_nodes(void)
log_debug("Unable to dynamically fixup USB nodes, please enable
CONFIG_OF_LIVE\n");
}
#endif /* OF_LIVE */
+void qcom_parse_memory(void);
+
#endif /* __QCOM_PRIV_H__ */
--
2.47.0
