Sync ufshci.h with the version found in the Linux v6.12
version commit adc218676eef ("Linux 6.12").

It adds new defines, and moves defines to the same place
as the Linux header.

No functional changes intended.

Signed-off-by: Neil Armstrong <neil.armstr...@linaro.org>
---
 drivers/ufs/ufshci.h | 285 +++++++++++++++++++++++++++++++++++++--------------
 1 file changed, 210 insertions(+), 75 deletions(-)

diff --git a/drivers/ufs/ufshci.h b/drivers/ufs/ufshci.h
index 
db30812b176f9e36529452e260b847241f97fdab..08af517b1028804e64602767f7a51bbfb083c59b
 100644
--- a/drivers/ufs/ufshci.h
+++ b/drivers/ufs/ufshci.h
@@ -8,61 +8,14 @@ enum {
        ALIGNED_UPIU_SIZE               = 512,
 };
 
-/* To accommodate UFS2.0 required Command type */
-enum {
-       UTP_CMD_TYPE_UFS_STORAGE        = 0x1,
-};
-
-enum {
-       UTP_SCSI_COMMAND                = 0x00000000,
-       UTP_NATIVE_UFS_COMMAND          = 0x10000000,
-       UTP_DEVICE_MANAGEMENT_FUNCTION  = 0x20000000,
-       UTP_REQ_DESC_INT_CMD            = 0x01000000,
-};
-
-/* UTP Transfer Request Data Direction (DD) */
-enum {
-       UTP_NO_DATA_TRANSFER    = 0x00000000,
-       UTP_HOST_TO_DEVICE      = 0x02000000,
-       UTP_DEVICE_TO_HOST      = 0x04000000,
-};
-
-/* Overall command status values */
-enum {
-       OCS_SUCCESS                     = 0x0,
-       OCS_INVALID_CMD_TABLE_ATTR      = 0x1,
-       OCS_INVALID_PRDT_ATTR           = 0x2,
-       OCS_MISMATCH_DATA_BUF_SIZE      = 0x3,
-       OCS_MISMATCH_RESP_UPIU_SIZE     = 0x4,
-       OCS_PEER_COMM_FAILURE           = 0x5,
-       OCS_ABORTED                     = 0x6,
-       OCS_FATAL_ERROR                 = 0x7,
-       OCS_INVALID_COMMAND_STATUS      = 0x0F,
-       MASK_OCS                        = 0x0F,
-};
-
-/* The maximum length of the data byte count field in the PRDT is 256KB */
-#define PRDT_DATA_BYTE_COUNT_MAX       (256 * 1024)
-/* The granularity of the data byte count field in the PRDT is 32-bit */
-#define PRDT_DATA_BYTE_COUNT_PAD       4
-
-/* Controller UFSHCI version */
-enum {
-       UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
-       UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
-       UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
-       UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
-       UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
-       UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
-       UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
-};
-
 /* UFSHCI Registers */
 enum {
        REG_CONTROLLER_CAPABILITIES             = 0x00,
+       REG_MCQCAP                              = 0x04,
        REG_UFS_VERSION                         = 0x08,
-       REG_CONTROLLER_DEV_ID                   = 0x10,
-       REG_CONTROLLER_PROD_ID                  = 0x14,
+       REG_EXT_CONTROLLER_CAPABILITIES         = 0x0C,
+       REG_CONTROLLER_PID                      = 0x10,
+       REG_CONTROLLER_MID                      = 0x14,
        REG_AUTO_HIBERNATE_IDLE_TIMER           = 0x18,
        REG_INTERRUPT_STATUS                    = 0x20,
        REG_INTERRUPT_ENABLE                    = 0x24,
@@ -94,20 +47,98 @@ enum {
        REG_UFS_CCAP                            = 0x100,
        REG_UFS_CRYPTOCAP                       = 0x104,
 
+       REG_UFS_MEM_CFG                         = 0x300,
+       REG_UFS_MCQ_CFG                         = 0x380,
+       REG_UFS_ESILBA                          = 0x384,
+       REG_UFS_ESIUBA                          = 0x388,
        UFSHCI_CRYPTO_REG_SPACE_SIZE            = 0x400,
 };
 
 /* Controller capability masks */
 enum {
-       MASK_TRANSFER_REQUESTS_SLOTS            = 0x0000001F,
+       MASK_TRANSFER_REQUESTS_SLOTS_SDB        = 0x0000001F,
+       MASK_TRANSFER_REQUESTS_SLOTS_MCQ        = 0x000000FF,
+       MASK_NUMBER_OUTSTANDING_RTT             = 0x0000FF00,
        MASK_TASK_MANAGEMENT_REQUEST_SLOTS      = 0x00070000,
+       MASK_EHSLUTRD_SUPPORTED                 = 0x00400000,
        MASK_AUTO_HIBERN8_SUPPORT               = 0x00800000,
        MASK_64_ADDRESSING_SUPPORT              = 0x01000000,
        MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
        MASK_UIC_DME_TEST_MODE_SUPPORT          = 0x04000000,
+       MASK_CRYPTO_SUPPORT                     = 0x10000000,
+       MASK_LSDB_SUPPORT                       = 0x20000000,
+       MASK_MCQ_SUPPORT                        = 0x40000000,
+};
+
+/* MCQ capability mask */
+enum {
+       MASK_EXT_IID_SUPPORT = 0x00000400,
+};
+
+enum {
+       REG_SQATTR              = 0x0,
+       REG_SQLBA               = 0x4,
+       REG_SQUBA               = 0x8,
+       REG_SQDAO               = 0xC,
+       REG_SQISAO              = 0x10,
+
+       REG_CQATTR              = 0x20,
+       REG_CQLBA               = 0x24,
+       REG_CQUBA               = 0x28,
+       REG_CQDAO               = 0x2C,
+       REG_CQISAO              = 0x30,
+};
+
+enum {
+       REG_SQHP                = 0x0,
+       REG_SQTP                = 0x4,
+       REG_SQRTC               = 0x8,
+       REG_SQCTI               = 0xC,
+       REG_SQRTS               = 0x10,
+};
+
+enum {
+       REG_CQHP                = 0x0,
+       REG_CQTP                = 0x4,
+};
+
+enum {
+       REG_CQIS                = 0x0,
+       REG_CQIE                = 0x4,
+};
+
+enum {
+       SQ_START                = 0x0,
+       SQ_STOP                 = 0x1,
+       SQ_ICU                  = 0x2,
+};
+
+enum {
+       SQ_STS                  = 0x1,
+       SQ_CUS                  = 0x2,
+};
+
+#define SQ_ICU_ERR_CODE_MASK           GENMASK(7, 4)
+#define UFS_MASK(mask, offset)         ((mask) << (offset))
+
+/* UFS Version 08h */
+#define MINOR_VERSION_NUM_MASK         UFS_MASK(0xFFFF, 0)
+#define MAJOR_VERSION_NUM_MASK         UFS_MASK(0xFFFF, 16)
+
+/* Controller UFSHCI version */
+enum {
+       UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
+       UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
+       UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
+       UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
+       UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
+       UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
+       UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
 };
 
-/* Interrupt Status 20h */
+/*
+ * IS - Interrupt Status - 20h
+ */
 #define UTP_TRANSFER_REQ_COMPL                 0x1
 #define UIC_DME_END_PT_RESET                   0x2
 #define UIC_ERROR                              0x4
@@ -122,25 +153,25 @@ enum {
 #define DEVICE_FATAL_ERROR                     0x800
 #define CONTROLLER_FATAL_ERROR                 0x10000
 #define SYSTEM_BUS_FATAL_ERROR                 0x20000
+#define CRYPTO_ENGINE_FATAL_ERROR              0x40000
+#define MCQ_CQ_EVENT_STATUS                    0x100000
 
-#define UFSHCD_UIC_PWR_MASK    (UIC_HIBERNATE_ENTER |\
-                               UIC_HIBERNATE_EXIT |\
+#define UFSHCD_UIC_HIBERN8_MASK        (UIC_HIBERNATE_ENTER |\
+                               UIC_HIBERNATE_EXIT)
+
+#define UFSHCD_UIC_PWR_MASK    (UFSHCD_UIC_HIBERN8_MASK |\
                                UIC_POWER_MODE)
 
-#define UFSHCD_UIC_MASK                (UIC_COMMAND_COMPL | UIC_POWER_MODE)
+#define UFSHCD_UIC_MASK                (UIC_COMMAND_COMPL | 
UFSHCD_UIC_PWR_MASK)
 
-#define UFSHCD_ERROR_MASK      (UIC_ERROR |\
-                               DEVICE_FATAL_ERROR |\
-                               CONTROLLER_FATAL_ERROR |\
-                               SYSTEM_BUS_FATAL_ERROR)
+#define UFSHCD_ERROR_MASK      (UIC_ERROR | INT_FATAL_ERRORS)
 
 #define INT_FATAL_ERRORS       (DEVICE_FATAL_ERROR |\
                                CONTROLLER_FATAL_ERROR |\
-                               SYSTEM_BUS_FATAL_ERROR)
+                               SYSTEM_BUS_FATAL_ERROR |\
+                               CRYPTO_ENGINE_FATAL_ERROR |\
+                               UIC_LINK_LOST)
 
-/* Host Controller Enable 0x34h */
-#define CONTROLLER_ENABLE      0x1
-#define CONTROLLER_DISABLE     0x0
 /* HCS - Host Controller Status 30h */
 #define DEVICE_PRESENT                         0x1
 #define UTP_TRANSFER_REQ_LIST_READY            0x2
@@ -163,6 +194,70 @@ enum {
        PWR_FATAL_ERROR = 0x05,
 };
 
+/* HCE - Host Controller Enable 34h */
+#define CONTROLLER_ENABLE      0x1
+#define CONTROLLER_DISABLE     0x0
+#define CRYPTO_GENERAL_ENABLE  0x2
+
+/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
+#define UIC_PHY_ADAPTER_LAYER_ERROR                    0x80000000
+#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK          0x1F
+#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK            0xF
+#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR            0x10
+
+/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
+#define UIC_DATA_LINK_LAYER_ERROR              0x80000000
+#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK    0xFFFF
+#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP    0x2
+#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP   0x4
+#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP    0x8
+#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF    0x20
+#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT      0x2000
+#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
+#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
+
+/* UECN - Host UIC Error Code Network Layer 40h */
+#define UIC_NETWORK_LAYER_ERROR                        0x80000000
+#define UIC_NETWORK_LAYER_ERROR_CODE_MASK      0x7
+#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE    0x1
+#define UIC_NETWORK_BAD_DEVICEID_ENC           0x2
+#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING  0x4
+
+/* UECT - Host UIC Error Code Transport Layer 44h */
+#define UIC_TRANSPORT_LAYER_ERROR              0x80000000
+#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK    0x7F
+#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE  0x1
+#define UIC_TRANSPORT_UNKNOWN_CPORTID          0x2
+#define UIC_TRANSPORT_NO_CONNECTION_RX         0x4
+#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING      0x8
+#define UIC_TRANSPORT_BAD_TC                   0x10
+#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW       0x20
+#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING    0x40
+
+/* UECDME - Host UIC Error Code DME 48h */
+#define UIC_DME_ERROR                  0x80000000
+#define UIC_DME_ERROR_CODE_MASK                0x1
+
+/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
+#define INT_AGGR_TIMEOUT_VAL_MASK              0xFF
+#define INT_AGGR_COUNTER_THRESHOLD_MASK                UFS_MASK(0x1F, 8)
+#define INT_AGGR_COUNTER_AND_TIMER_RESET       0x10000
+#define INT_AGGR_STATUS_BIT                    0x100000
+#define INT_AGGR_PARAM_WRITE                   0x1000000
+#define INT_AGGR_ENABLE                                0x80000000
+
+/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
+#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT     0x1
+
+/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
+#define UTP_TASK_REQ_LIST_RUN_STOP_BIT         0x1
+
+/* REG_UFS_MEM_CFG - Global Config Registers 300h */
+#define MCQ_MODE_SELECT        BIT(0)
+
+/* CQISy - CQ y Interrupt Status Register  */
+#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS      0x1
+
 /* UICCMD - UIC Command */
 #define COMMAND_OPCODE_MASK            0xFF
 #define GEN_SELECTOR_INDEX_MASK                0xFFFF
@@ -171,7 +266,7 @@ enum {
 #define RESET_LEVEL                    0xFF
 
 #define ATTR_SET_TYPE_MASK             UFS_MASK(0xFF, 16)
-#define CFG_RESULT_CODE_MASK           0xFF
+#define CONFIG_RESULT_CODE_MASK                0xFF
 #define GENERIC_ERROR_CODE_MASK                0xFF
 
 /* GenSelectorIndex calculation macros for M-PHY attributes */
@@ -190,12 +285,6 @@ enum link_status {
        UFSHCD_LINK_IS_UP       = 2,
 };
 
-#define UIC_ARG_MIB_SEL(attr, sel)     ((((attr) & 0xFFFF) << 16) |\
-                                        ((sel) & 0xFFFF))
-#define UIC_ARG_MIB(attr)              UIC_ARG_MIB_SEL(attr, 0)
-#define UIC_ARG_ATTR_TYPE(t)           (((t) & 0xFF) << 16)
-#define UIC_GET_ATTR_ID(v)             (((v) >> 16) & 0xFFFF)
-
 /* UIC Commands */
 enum uic_cmd_dme {
        UIC_CMD_DME_GET                 = 0x01,
@@ -231,11 +320,57 @@ enum {
 
 #define MASK_UIC_COMMAND_RESULT                        0xFF
 
-/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
-#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT     0x1
+#define INT_AGGR_COUNTER_THLD_VAL(c)   (((c) & 0x1F) << 8)
+#define INT_AGGR_TIMEOUT_VAL(t)                (((t) & 0xFF) << 0)
+
+/*
+ * Request Descriptor Definitions
+ */
+
+/* To accommodate UFS2.0 required Command type */
+enum {
+       UTP_CMD_TYPE_UFS_STORAGE        = 0x1,
+};
+
+enum {
+       UTP_SCSI_COMMAND                = 0x00000000,
+       UTP_REQ_DESC_INT_CMD            = 0x01000000,
+       UTP_NATIVE_UFS_COMMAND          = 0x10000000,
+       UTP_DEVICE_MANAGEMENT_FUNCTION  = 0x20000000,
+};
+
+/* UTP Transfer Request Data Direction (DD) */
+enum utp_data_direction {
+       UTP_NO_DATA_TRANSFER    = 0,
+       UTP_HOST_TO_DEVICE      = 1,
+       UTP_DEVICE_TO_HOST      = 2,
+};
+
+/* Overall command status values */
+enum utp_ocs {
+       OCS_SUCCESS                     = 0x0,
+       OCS_INVALID_CMD_TABLE_ATTR      = 0x1,
+       OCS_INVALID_PRDT_ATTR           = 0x2,
+       OCS_MISMATCH_DATA_BUF_SIZE      = 0x3,
+       OCS_MISMATCH_RESP_UPIU_SIZE     = 0x4,
+       OCS_PEER_COMM_FAILURE           = 0x5,
+       OCS_ABORTED                     = 0x6,
+       OCS_FATAL_ERROR                 = 0x7,
+       OCS_DEVICE_FATAL_ERROR          = 0x8,
+       OCS_INVALID_CRYPTO_CONFIG       = 0x9,
+       OCS_GENERAL_CRYPTO_ERROR        = 0xA,
+       OCS_INVALID_COMMAND_STATUS      = 0x0F,
+};
+
+enum {
+       MASK_OCS                        = 0x0F,
+};
+
+/* The maximum length of the data byte count field in the PRDT is 256KB */
+#define PRDT_DATA_BYTE_COUNT_MAX       SZ_256K
+/* The granularity of the data byte count field in the PRDT is 32-bit */
+#define PRDT_DATA_BYTE_COUNT_PAD       4
 
-/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
-#define UTP_TASK_REQ_LIST_RUN_STOP_BIT         0x1
 
 struct ufshcd_sg_entry {
        __le32    base_addr;

-- 
2.34.1

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