Hi Tom,
The following changes since commit 56accc56b9aab87ef4809ccc588e1257969cd271:
bios_emulator: fix first argument of pci_{read,write}_config_* function calls
(2024-11-04 18:01:58 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to d5f5e778183d5908caa2954b9438614252b806dd:
riscv: Introduce configuration for 64bit version Microblaze V (2024-11-06
19:42:54 +0800)
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23239
----------------------------------------------------------------
- configs: visionfive2 defconfig: re-enable SPL_SYS_MMCSD_RAW_MODE
- driver: sifive ccache: enable TRUNKCLOCKGATE & REGIONCLOCKGATE
- board: support 64bit Microblaze V
----------------------------------------------------------------
Andreas Schwab (1):
configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE
Michal Simek (3):
xilinx: mbv: Place DTB by default to DDR location
xilinx: mbv: Align smode_defconfig with upstream QEMU
riscv: Introduce configuration for 64bit version Microblaze V
Nick Hu (1):
driver: sifive ccache: enable TRUNKCLOCKGATE and REGIONCLOCKGATE
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/xilinx-mbv64.dts | 99 ++++++++++++++++++++++++++++++++++
board/xilinx/Kconfig | 2 +-
configs/starfive_visionfive2_defconfig | 3 ++
configs/xilinx_mbv32_smode_defconfig | 12 ++---
configs/xilinx_mbv64_defconfig | 44 +++++++++++++++
configs/xilinx_mbv64_smode_defconfig | 48 +++++++++++++++++
drivers/cache/cache-sifive-ccache.c | 33 ++++++++++--
8 files changed, 232 insertions(+), 10 deletions(-)
create mode 100644 arch/riscv/dts/xilinx-mbv64.dts
create mode 100644 configs/xilinx_mbv64_defconfig
create mode 100644 configs/xilinx_mbv64_smode_defconfig
Best regards,
Leo
