When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.
Fixes: 387d4275ab0e ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker <paul.barker...@bp.renesas.com>
---
arch/arm/mach-renesas/include/mach/rzg2l.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-renesas/include/mach/rzg2l.h
b/arch/arm/mach-renesas/include/mach/rzg2l.h
index 057df5cb9d46..c49a71a6dd41 100644
--- a/arch/arm/mach-renesas/include/mach/rzg2l.h
+++ b/arch/arm/mach-renesas/include/mach/rzg2l.h
@@ -8,6 +8,6 @@
#define __ASM_ARCH_RZG2L_H
#define GICD_BASE 0x11900000
-#define GICR_BASE 0x11960000
+#define GICR_BASE 0x11940000
#endif /* __ASM_ARCH_RZG2L_H */
--
2.43.0
