Signed-off-by: Simon Glass <s...@chromium.org>
---
arch/arm/cpu/armv7/tegra2/ap20.c | 47 +++++++++-------------------
arch/arm/include/asm/arch-tegra2/clk_rst.h | 39 ++---------------------
board/nvidia/common/board.c | 13 ++++---
3 files changed, 25 insertions(+), 74 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index a9bfd6a..7da00cd 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -24,6 +24,7 @@
#include "ap20.h"
#include <asm/io.h>
#include <asm/arch/tegra2.h>
+#include <asm/arch/bitfield.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/pmc.h>
@@ -40,23 +41,22 @@ void init_pllx(void)
u32 reg;
/* If PLLX is already enabled, just return */
- reg = readl(&pll->pll_base);
- if (reg & PLL_ENABLE_BIT)
+ if (bf_readl(PLL_ENABLE, &pll->pll_base))
return;
/* Set PLLX_MISC */
- reg = CPCON; /* CPCON[11:8] = 0001 */
+ reg = bf_pack(PLL_CPCON, 1);
writel(reg, &pll->pll_misc);
/* Use 12MHz clock here */
- reg = (PLL_BYPASS_BIT | PLL_DIVM_VALUE);
- reg |= (1000 << 8); /* DIVN = 0x3E8 */
+ reg = bf_pack(PLL_BYPASS, 1) | bf_pack(PLL_DIVM, 12);
+ reg |= bf_pack(PLL_DIVN, 1000);
writel(reg, &pll->pll_base);
- reg |= PLL_ENABLE_BIT;
+ reg |= bf_pack(PLL_ENABLE, 1);
writel(reg, &pll->pll_base);
- reg &= ~PLL_BYPASS_BIT;
+ reg &= ~bf_mask(PLL_BYPASS);
writel(reg, &pll->pll_base);
}
@@ -90,17 +90,12 @@ static void enable_cpu_clock(int enable)
* always stop the clock to CPU 1.
*/
clk = readl(&clkrst->crc_clk_cpu_cmplx);
- clk |= CPU1_CLK_STP;
-
- if (enable) {
- /* Unstop the CPU clock */
- clk &= ~CPU0_CLK_STP;
- } else {
- /* Stop the CPU clock */
- clk |= CPU0_CLK_STP;
- }
+ clk |= bf_pack(CPU1_CLK_STP, 1);
+ /* Stop/Unstop the CPU clock */
+ bf_update(CPU0_CLK_STP, clk, enable == 0);
writel(clk, &clkrst->crc_clk_cpu_cmplx);
+
clock_enable(PERIPH_ID_CPU);
}
@@ -176,9 +171,6 @@ static void enable_cpu_power_rail(void)
static void reset_A9_cpu(int reset)
{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 cpu;
-
/*
* NOTE: Regardless of whether the request is to hold the CPU in reset
* or take it out of reset, every processor in the CPU complex
@@ -187,19 +179,10 @@ static void reset_A9_cpu(int reset)
* are multiple processors in the CPU complex.
*/
- /* Hold CPU 1 in reset */
- cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1;
- writel(cpu, &clkrst->crc_cpu_cmplx_set);
-
- if (reset) {
- /* Now place CPU0 into reset */
- cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0;
- writel(cpu, &clkrst->crc_cpu_cmplx_set);
- } else {
- /* Take CPU0 out of reset */
- cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0;
- writel(cpu, &clkrst->crc_cpu_cmplx_clr);
- }
+ /* Hold CPU 1 in reset, and CPU 0 if asked */
+ reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
+ reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
+ reset);
/* Enable/Disable master CPU reset */
reset_set_enable(PERIPH_ID_CPU, reset);
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h
b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index f51300e..a8c6fb3 100644
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -141,42 +141,9 @@ struct clk_rst_ctlr {
uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
};
-#define PLL_BYPASS_BIT (1 << 31)
-#define PLL_ENABLE_BIT (1 << 30)
-#define PLL_BASE_OVRRIDE_BIT (1 << 28)
-#define PLL_DIVP_VALUE (1 << 20) /* post divider, b22:20 */
-#define PLL_DIVM_VALUE 0x0C /* input divider, b4:0 */
-
-#define SWR_UARTD_RST (1 << 1)
-#define CLK_ENB_UARTD (1 << 1)
-#define SWR_UARTA_RST (1 << 6)
-#define CLK_ENB_UARTA (1 << 6)
-
-#define SWR_CPU_RST (1 << 0)
-#define CLK_ENB_CPU (1 << 0)
-#define SWR_CSITE_RST (1 << 9)
-#define CLK_ENB_CSITE (1 << 9)
-
-#define SET_CPURESET0 (1 << 0)
-#define SET_DERESET0 (1 << 4)
-#define SET_DBGRESET0 (1 << 12)
-
-#define SET_CPURESET1 (1 << 1)
-#define SET_DERESET1 (1 << 5)
-#define SET_DBGRESET1 (1 << 13)
-
-#define CLR_CPURESET0 (1 << 0)
-#define CLR_DERESET0 (1 << 4)
-#define CLR_DBGRESET0 (1 << 12)
-
-#define CLR_CPURESET1 (1 << 1)
-#define CLR_DERESET1 (1 << 5)
-#define CLR_DBGRESET1 (1 << 13)
-
-#define CPU0_CLK_STP (1 << 8)
-#define CPU1_CLK_STP (1 << 9)
-
-#define CPCON (1 << 8)
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
+#define CPU1_CLK_STP_RANGE 9 : 9
+#define CPU0_CLK_STP_RANGE 8 : 8
/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
#define PLL_BYPASS_RANGE 31 : 31
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index f07328e..ac2e3f8 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
+#include <asm/arch/bitfield.h>
#include <asm/arch/tegra2.h>
#include <asm/arch/sys_proto.h>
@@ -78,20 +79,20 @@ static void clock_init_uart(void)
u32 reg;
reg = readl(&pll->pll_base);
- if (!(reg & PLL_BASE_OVRRIDE_BIT)) {
+ if (!(reg & bf_mask(PLL_BASE_OVRRIDE))) {
/* Override pllp setup for 216MHz operation. */
- reg = (PLL_BYPASS_BIT | PLL_BASE_OVRRIDE_BIT | PLL_DIVP_VALUE);
- reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM_VALUE);
+ reg = bf_mask(PLL_BYPASS) | bf_mask(PLL_BASE_OVRRIDE) |
+ bf_pack(PLL_DIVP, 1) | bf_pack(PLL_DIVM, 0xc);
+ reg |= bf_pack(PLL_DIVN, NVRM_PLLP_FIXED_FREQ_KHZ / 500);
writel(reg, &pll->pll_base);
- reg |= PLL_ENABLE_BIT;
+ reg |= bf_mask(PLL_ENABLE);
writel(reg, &pll->pll_base);
- reg &= ~PLL_BYPASS_BIT;
+ reg &= ~bf_mask(PLL_BYPASS);
writel(reg, &pll->pll_base);
}
- /* Now do the UART reset/clock enable */
#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
/* Assert UART reset and enable clock */
reset_set_enable(PERIPH_ID_UART1, 1);
--
1.7.3.1
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