Hi Peng,
Le ven. 11 oct. 2024 à 06:20, Peng Fan (OSS) <peng....@oss.nxp.com> a écrit :
>
> From: Peng Fan <peng....@nxp.com>
>
> i.MX8MP SDHC use CLK_IMX8MP_DUMMY clk entry. Without the clk, the bulk
> api will return failure.
>
> The correct entry should be replaced with IMX8MP_IPG_ROOT clk in device
> tree. This will be done in Kernel device tree and sync to U-Boot in
> future.
>
> Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk
> API")
> Reported-by: Gilles Talis <gilles.ta...@nxp.com>
> Signed-off-by: Peng Fan <peng....@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mp.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 34d91cd6880..1d04090ca00 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -197,6 +197,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
>
> base = (void *)ANATOP_BASE_ADDR;
>
> + clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
> +
> clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base
> + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base +
> 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base
> + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> --
> 2.35.3
>
I confirm that the issue I was seeing on my i.MX8MP-based board goes
away with this patch.
Tested-by: Gilles TALIS <gilles.ta...@gmail.com>
