Device tree for this board can be deleted. Device tree location
now points to the freescale/ directory.
Use absolute path to PMIC node entry and its regulators as
device tree in kernel does not provide corresponding labels
Signed-off-by: Gilles Talis <gilles.ta...@gmail.com>
---
arch/arm/dts/Makefile | 1 -
arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi | 16 +-
arch/arm/dts/imx8mp-debix-model-a.dts | 507 ------------------
arch/arm/mach-imx/imx8m/Kconfig | 1 +
configs/imx8mp_debix_model_a_defconfig | 2 +-
5 files changed, 10 insertions(+), 517 deletions(-)
delete mode 100644 arch/arm/dts/imx8mp-debix-model-a.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 65176c8fb8..73efdcf975 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -967,7 +967,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
- imx8mp-debix-model-a.dtb \
imx8mp-dhcom-drc02.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
index 33bd89a843..d5bd9f591e 100644
--- a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
@@ -20,6 +20,14 @@
};
};
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+ bootph-pre-ram;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ bootph-pre-ram;
+};
+
&crypto {
bootph-pre-ram;
};
@@ -88,14 +96,6 @@
bootph-pre-ram;
};
-&pmic {
- bootph-pre-ram;
-
- regulators {
- bootph-pre-ram;
- };
-};
-
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts
b/arch/arm/dts/imx8mp-debix-model-a.dts
deleted file mode 100644
index 58dae612b4..0000000000
--- a/arch/arm/dts/imx8mp-debix-model-a.dts
+++ /dev/null
@@ -1,507 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 NXP
- * Copyright 2022 Ideas on Board Oy
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/usb/pd.h>
-
-#include "imx8mp.dtsi"
-
-/ {
- model = "Polyhex Debix Model A i.MX8MPlus board";
- compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix",
"fsl,imx8mp";
-
- chosen {
- stdout-path = &uart2;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_led>;
-
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-connection-type = "rgmii-id";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 { /* RTL8211E */
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
- reset-assert-us = <20>;
- reset-deassert-us = <200000>;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic: pmic@25 {
- compatible = "nxp,pca9450c";
- reg = <0x25>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
-
- regulators {
- buck1: BUCK1 {
- regulator-name = "BUCK1";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-name = "BUCK2";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- buck4: BUCK4{
- regulator-name = "BUCK4";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5: BUCK5{
- regulator-name = "BUCK5";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6: BUCK6 {
- regulator-name = "BUCK6";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1: LDO1 {
- regulator-name = "LDO1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2: LDO2 {
- regulator-name = "LDO2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3: LDO3 {
- regulator-name = "LDO3";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4: LDO4 {
- regulator-name = "LDO4";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5: LDO5 {
- regulator-name = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rtc_int>;
- };
-};
-
-&i2c6 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c6>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-&uart2 {
- /* console */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-/* SD Card */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC
0x3
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO
0x3
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0
0x91
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1
0x91
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2
0x91
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3
0x91
-
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL
0x91
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0
0x1f
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1
0x1f
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2
0x1f
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3
0x1f
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL
0x1f
-
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
- MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN
0x1f
- MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT
0x1f
- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18
0x19
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC
0x3
- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO
0x3
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0
0x91
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1
0x91
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2
0x91
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3
0x91
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC
0x91
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL
0x91
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0
0x1f
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1
0x1f
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2
0x1f
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3
0x1f
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL
0x1f
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC
0x1f
- MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT
0x1f
- MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN
0x1f
- MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19
0x19
- >;
- };
-
- pinctrl_gpio_led: gpioledgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16
0x19
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL
0x400001c2
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA
0x400001c2
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL
0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA
0x400001c2
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL
0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA
0x400001c2
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL
0x400001c3
- MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA
0x400001c3
- >;
- };
-
- pinctrl_i2c6: i2c6grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL
0x400001c3
- MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA
0x400001c3
- >;
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
0x41
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19
0x41
- >;
- };
-
- pinctrl_rtc_int: rtcintgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11
0x140
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX
0x14f
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX
0x14f
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX
0x49
- MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX
0x49
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX
0x49
- MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX
0x49
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK
0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD
0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0
0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1
0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2
0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3
0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK
0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD
0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0
0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1
0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2
0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3
0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK
0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD
0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0
0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1
0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2
0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3
0x1d6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12
0x1c4
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
0x1d6
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B
0xc6
- >;
- };
-};
-
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d1fdaec704..9d1fabe91c 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -197,6 +197,7 @@ config TARGET_IMX8MP_DEBIX_MODEL_A
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MP_DH_DHCOM_PDK2
bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
diff --git a/configs/imx8mp_debix_model_a_defconfig
b/configs/imx8mp_debix_model_a_defconfig
index dcc529f9fc..9f75ab1477 100644
--- a/configs/imx8mp_debix_model_a_defconfig
+++ b/configs/imx8mp_debix_model_a_defconfig
@@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-debix-model-a"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-debix-model-a"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_DEBIX_MODEL_A=y
CONFIG_SYS_MONITOR_LEN=524288
base-commit: 93b9cd792089e536f2bfa85d9903fd4798209f76
--
2.43.0
