From: Dinesh Maniyam <dinesh.mani...@intel.com> The patch is to ensure ddr memory is updated with the data from dcache, This would help to ensure cdma always reading the latest dma descriptor in ddr memory.
Signed-off-by: Dinesh Maniyam <dinesh.mani...@intel.com> --- drivers/mtd/nand/raw/cadence_nand.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/raw/cadence_nand.c b/drivers/mtd/nand/raw/cadence_nand.c index 108e1fa965..429a5e8017 100644 --- a/drivers/mtd/nand/raw/cadence_nand.c +++ b/drivers/mtd/nand/raw/cadence_nand.c @@ -429,6 +429,10 @@ cadence_nand_cdma_desc_prepare(struct cadence_nand_info *cadence, cdma_desc->command_type = ctype; cdma_desc->ctrl_data_ptr = ctrl_data_ptr; + + flush_cache((dma_addr_t)cadence->cdma_desc, + ROUND(sizeof(struct cadence_nand_cdma_desc), + ARCH_DMA_MINALIGN)); } static u8 cadence_nand_check_desc_error(struct cadence_nand_info *cadence, -- 2.26.2