Hi Patrick,
On Wed, 11 Sept 2024 at 00:25, Patrick Rudolph
<patrick.rudo...@9elements.com> wrote:
>
> Add a generic driver that binds to armv8 CPU nodes.
>
> TEST: Booted on QEMU sbsa and verify the driver binds to CPU nodes.
> Confirmed with FWTS that all ACPI processor devices are present.
>
> Signed-off-by: Patrick Rudolph <patrick.rudo...@9elements.com>
> Cc: Tom Rini <tr...@konsulko.com>
> Cc: Simon Glass <s...@chromium.org>
> ---
> drivers/cpu/Kconfig | 6 +++
> drivers/cpu/Makefile | 2 +
> drivers/cpu/armv8_cpu.c | 90 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 98 insertions(+)
> create mode 100644 drivers/cpu/armv8_cpu.c
>
> diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
> index 5c06cd9f60..9c0df331d7 100644
> --- a/drivers/cpu/Kconfig
> +++ b/drivers/cpu/Kconfig
> @@ -26,6 +26,12 @@ config CPU_RISCV
> help
> Support CPU cores for RISC-V architecture.
>
> +config CPU_ARMV8
> + bool "Enable generic ARMv8 CPU driver"
> + depends on CPU && ARM64
> + help
> + Support CPU cores for armv8 architecture.
add more detail (as per Peter's comments)
> +
> config CPU_MICROBLAZE
> bool "Enable Microblaze CPU driver"
> depends on CPU && MICROBLAZE
> diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
> index bc75d9b974..773395693a 100644
> --- a/drivers/cpu/Makefile
> +++ b/drivers/cpu/Makefile
> @@ -6,10 +6,12 @@
>
> obj-$(CONFIG_CPU) += cpu-uclass.o
>
> +
drop
> obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
> obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
> obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
> obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
> +obj-$(CONFIG_CPU_ARMV8) += armv8_cpu.o
> obj-$(CONFIG_CPU_IMX) += imx8_cpu.o
> obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
> obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
> diff --git a/drivers/cpu/armv8_cpu.c b/drivers/cpu/armv8_cpu.c
> new file mode 100644
> index 0000000000..08b8d45f6f
> --- /dev/null
> +++ b/drivers/cpu/armv8_cpu.c
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 Broadcom.
> + */
> +#include <acpi/acpigen.h>
> +#include <asm/armv8/cpu.h>
> +#include <cpu.h>
> +#include <dm.h>
> +#include <dm/acpi.h>
> +#include <asm/io.h>
> +#include <linux/bitops.h>
> +#include <linux/printk.h>
> +#include <linux/sizes.h>
> +
> +static int armv8_cpu_get_desc(const struct udevice *dev, char *buf, int size)
> +{
> + int cpuid;
> +
> + cpuid = (read_midr() & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT;
> +
> + snprintf(buf, size, "CPU MIDR %04x", cpuid);
> +
> + return 0;
> +}
> +
> +static int armv8_cpu_get_info(const struct udevice *dev,
> + struct cpu_info *info)
> +{
> + info->cpu_freq = 0;
> + info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
> +
> + return 0;
> +}
> +
> +static int armv8_cpu_get_count(const struct udevice *dev)
> +{
> + ofnode node;
> + int num = 0;
> +
> + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
> + const char *device_type;
> +
> + if (!ofnode_is_enabled(node))
> + continue;
> +
> + device_type = ofnode_read_string(node, "device_type");
> + if (!device_type)
> + continue;
> +
> + if (!strcmp(device_type, "cpu"))
> + num++;
> + }
> +
> + return num;
Isn't this uclass_id_count(UCLASS_CPU) ?
> +}
> +
> +#ifdef CONFIG_ACPIGEN
> +static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx
> *ctx)
> +{
> + uint core_id = dev_seq(dev);
> +
> + acpigen_write_processor_device(ctx, core_id);
error checking?
> +
> + return 0;
> +}
> +
> +struct acpi_ops armv8_cpu_acpi_ops = {
> + .fill_ssdt = acpi_cpu_fill_ssdt,
> +};
> +#endif
> +
> +static const struct cpu_ops cpu_ops = {
> + .get_count = armv8_cpu_get_count,
> + .get_desc = armv8_cpu_get_desc,
> + .get_info = armv8_cpu_get_info,
> +};
> +
> +static const struct udevice_id cpu_ids[] = {
> + { .compatible = "arm,armv8" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(arm_cpu) = {
> + .name = "arm-cpu",
> + .id = UCLASS_CPU,
> + .of_match = cpu_ids,
> + .ops = &cpu_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> + ACPI_OPS_PTR(&armv8_cpu_acpi_ops)
> +};
> --
> 2.46.0
>
Regards,
Simon
