The arrays containing the mux selectors need to be of const pointer
to const char.
Signed-off-by: Michael Trimarchi <mich...@amarulasolutions.com>
---
drivers/clk/imx/clk-imx8mn.c | 142 ++++++++++++++++++++---------------
1 file changed, 81 insertions(+), 61 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index bfd1677520..8911e342f1 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -16,106 +16,126 @@
static u32 share_count_nand;
-static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy",
"dummy", };
-static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
-static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
-static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
-static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
-static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy",
"dummy", "dummy", };
+static const char * const dram_pll_bypass_sels[] = {"dram_pll",
"dram_pll_ref_sel", };
+static const char * const arm_pll_bypass_sels[] = {"arm_pll",
"arm_pll_ref_sel", };
+static const char * const sys_pll1_bypass_sels[] = {"sys_pll1",
"sys_pll1_ref_sel", };
+static const char * const sys_pll2_bypass_sels[] = {"sys_pll2",
"sys_pll2_ref_sel", };
+static const char * const sys_pll3_bypass_sels[] = {"sys_pll3",
"sys_pll3_ref_sel", };
-static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out",
"sys_pll2_500m", "sys_pll2_1000m",
- "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
+static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out",
"sys_pll2_500m",
+ "sys_pll2_1000m",
"sys_pll1_800m", "sys_pll1_400m",
+ "audio_pll1_out",
"sys_pll3_out", };
-static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m",
"sys_pll1_800m", "sys_pll1_400m",
- "sys_pll2_125m", "sys_pll3_out",
"audio_pll1_out", "video_pll_out", };
+static const char * const imx8mn_ahb_sels[] = {"clock-osc-24m",
"sys_pll1_133m", "sys_pll1_800m",
+ "sys_pll1_400m",
"sys_pll2_125m", "sys_pll3_out",
+ "audio_pll1_out",
"video_pll_out", };
-static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m",
"sys_pll1_800m", "sys_pll2_250m",
- "sys_pll2_200m", "audio_pll1_out",
"video_pll_out", "sys_pll3_out", };
+static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m",
"sys_pll1_266m", "sys_pll1_800m",
+ "sys_pll2_250m",
"sys_pll2_200m", "audio_pll1_out",
+ "video_pll_out",
"sys_pll3_out", };
#ifndef CONFIG_SPL_BUILD
-static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m",
"sys_pll2_50m", "sys_pll2_100m",
- "sys_pll1_160m", "audio_pll1_out",
"video_pll_out", "clk_ext4", };
+static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m",
"sys_pll2_125m", "sys_pll2_50m",
+ "sys_pll2_100m",
"sys_pll1_160m", "audio_pll1_out",
+ "video_pll_out",
"clk_ext4", };
-static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4",
"video_pll_out", };
+static const char * const imx8mn_enet_timer_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "audio_pll1_out",
+ "clk_ext1", "clk_ext2",
"clk_ext3",
+ "clk_ext4",
"video_pll_out", };
-static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m",
"sys_pll2_125m", "sys_pll2_200m",
- "sys_pll2_500m", "audio_pll1_out",
"video_pll_out", "audio_pll2_out", };
+static const char * const imx8mn_enet_phy_sels[] = {"clock-osc-24m",
"sys_pll2_50m", "sys_pll2_125m",
+ "sys_pll2_200m",
"sys_pll2_500m", "audio_pll1_out",
+ "video_pll_out",
"audio_pll2_out", };
#endif
-static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m",
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
- "sys_pll1_133m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll1_out", };
+static const char * const imx8mn_nand_usdhc_sels[] = {"clock-osc-24m",
"sys_pll1_266m", "sys_pll1_800m",
+ "sys_pll2_200m",
"sys_pll1_133m", "sys_pll3_out",
+ "sys_pll2_250m",
"audio_pll1_out", };
static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m",
"sys_pll2_500m", "sys_pll1_800m",
- "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2",
- "clk_ext4", "audio_pll2_out", };
+ "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2",
+ "clk_ext4",
"audio_pll2_out", };
-static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m",
"sys_pll1_800m", "sys_pll2_500m",
- "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
+static const char * const imx8mn_usdhc1_sels[] = {"clock-osc-24m",
"sys_pll1_400m", "sys_pll1_800m",
+ "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m",
+ "audio_pll2_out",
"sys_pll1_100m", };
-static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m",
"sys_pll1_800m", "sys_pll2_500m",
- "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
+static const char * const imx8mn_usdhc2_sels[] = {"clock-osc-24m",
"sys_pll1_400m", "sys_pll1_800m",
+ "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m",
+ "audio_pll2_out",
"sys_pll1_100m", };
#if CONFIG_IS_ENABLED(DM_SPI)
-static const char *imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m",
"sys_pll1_40m",
- "sys_pll1_160m", "sys_pll1_800m",
"sys_pll3_out",
- "sys_pll2_250m", "audio_pll2_out", };
+static const char * const imx8mn_ecspi1_sels[] = {"clock-osc-24m",
"sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m",
"audio_pll2_out", };
-static const char *imx8mn_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m",
"sys_pll1_40m",
- "sys_pll1_160m", "sys_pll1_800m",
"sys_pll3_out",
- "sys_pll2_250m", "audio_pll2_out", };
+static const char * const imx8mn_ecspi2_sels[] = {"clock-osc-24m",
"sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m",
"audio_pll2_out", };
-static const char *imx8mn_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m",
"sys_pll1_40m",
- "sys_pll1_160m", "sys_pll1_800m",
"sys_pll3_out",
- "sys_pll2_250m", "audio_pll2_out", };
+static const char * const imx8mn_ecspi3_sels[] = {"clock-osc-24m",
"sys_pll2_200m", "sys_pll1_40m",
+ "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out",
+ "sys_pll2_250m",
"audio_pll2_out", };
#endif
-static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char * const imx8mn_i2c1_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_pll2_50m",
+ "sys_pll3_out",
"audio_pll1_out", "video_pll_out",
+ "audio_pll2_out",
"sys_pll1_133m", };
-static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char * const imx8mn_i2c2_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_pll2_50m",
+ "sys_pll3_out",
"audio_pll1_out", "video_pll_out",
+ "audio_pll2_out",
"sys_pll1_133m", };
-static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char * const imx8mn_i2c3_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_pll2_50m",
+ "sys_pll3_out",
"audio_pll1_out", "video_pll_out",
+ "audio_pll2_out",
"sys_pll1_133m", };
-static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m",
"sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_pll2_50m",
+ "sys_pll3_out",
"audio_pll1_out", "video_pll_out",
+ "audio_pll2_out",
"sys_pll1_133m", };
#ifndef CONFIG_SPL_BUILD
-static const char *imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll_out", };
+static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext1",
+ "sys_pll1_80m",
"video_pll_out", };
-static const char *imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll_out", };
+static const char * const imx8mn_pwm2_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext1",
+ "sys_pll1_80m",
"video_pll_out", };
-static const char *imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll_out", };
+static const char * const imx8mn_pwm3_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext2",
+ "sys_pll1_80m",
"video_pll_out", };
-static const char *imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll_out", };
+static const char * const imx8mn_pwm4_sels[] = {"clock-osc-24m",
"sys_pll2_100m", "sys_pll1_160m",
+ "sys_pll1_40m", "sys_pll3_out",
"clk_ext2",
+ "sys_pll1_80m",
"video_pll_out", };
#endif
-static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m",
"sys_pll1_160m", "m7_alt_pll",
- "sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m", };
+static const char * const imx8mn_wdog_sels[] = {"clock-osc-24m",
"sys_pll1_133m", "sys_pll1_160m",
+ "m7_alt_pll", "sys_pll2_125m",
"sys_pll3_out",
+ "sys_pll1_80m",
"sys_pll2_166m", };
-static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m",
"sys_pll1_800m", "sys_pll2_500m",
- "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_clk", "sys_pll1_100m", };
+static const char * const imx8mn_usdhc3_sels[] = {"clock-osc-24m",
"sys_pll1_400m", "sys_pll1_800m",
+ "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m",
+ "audio_pll2_clk",
"sys_pll1_100m", };
-static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m",
"sys_pll2_333m", "sys_pll2_500m",
- "audio_pll2_out", "sys_pll1_266m",
"sys_pll3_out", "sys_pll1_100m", };
+static const char * const imx8mn_qspi_sels[] = {"clock-osc-24m",
"sys_pll1_400m", "sys_pll2_333m",
+ "sys_pll2_500m",
"audio_pll2_out", "sys_pll1_266m",
+ "sys_pll3_out",
"sys_pll1_100m", };
static const char * const imx8mn_nand_sels[] = {"clock-osc-24m",
"sys_pll2_500m", "audio_pll1_out",
"sys_pll1_400m",
"audio_pll2_out", "sys_pll3_out",
"sys_pll2_250m",
"video_pll_out", };
static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m",
"sys_pll1_100m", "sys_pll1_40m",
- "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2",
- "clk_ext3", "audio_pll2_out", };
+ "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2",
+ "clk_ext3",
"audio_pll2_out", };
static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m",
"sys_pll1_100m", "sys_pll1_40m",
- "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2",
- "clk_ext3", "audio_pll2_out", };
+ "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2",
+ "clk_ext3",
"audio_pll2_out", };
static int imx8mn_clk_probe(struct udevice *dev)
{
--
2.43.0
