From: Apurva Nandan <a-nan...@ti.com> This virtual clock mux configuration enables the use of dynamic frequency scaling on A72 clock ID 202 by setting up the required register.
Signed-off-by: Apurva Nandan <a-nan...@ti.com> Signed-off-by: Neha Malcom Francis <n-fran...@ti.com> --- Boot logs: https://gist.github.com/nehamalcom/138d25fe32d4d80af3e0e4c19c1b18e0 arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 9655ca21d02..25e4b4c7663 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -28,7 +28,8 @@ <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 342 0>; + assigned-clock-parents= <0>, <0>, <&k3_clks 342 2>; assigned-clock-rates = <2000000000>, <200000000>; ti,sci = <&dmsc>; ti,sci-proc-id = <32>; -- 2.34.1
