The current NAND timings, introduced in commit
a3f88293ddd13facd734769c1664d35ab4ed681f da850evm: setup the NAND flash
timings , incorrectly set WSTROBE and TA to 0. A more recent inspection of the
values set by the Linux kernel indicates that these should be set to 1.
Set the WSTROBE and TA field of the EMIFA cycle-count timings configuration to
1 to match the values set by linux.
Signed-off-by: Ben Gardiner <bengardi...@nanometrics.ca>
CC: Stefano Babic <sba...@denx.de>
CC: Sandeep Paulraj <s-paul...@ti.com>
CC: Scott Wood <scottw...@freescale.com>
---
board/davinci/da8xxevm/da850evm.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/davinci/da8xxevm/da850evm.c
b/board/davinci/da8xxevm/da850evm.c
index b088c9c..73eaa48 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -179,12 +179,12 @@ int board_init(void)
* Linux kernel @ 25MHz EMIFA
*/
writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(0) |
+ DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
- DAVINCI_ABCR_TA(0) |
+ DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab2cr); /* CS3 */
#endif
--
1.7.1
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